TMS320C6720RFP300 datasheet(18/118 Pages) TI

18 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

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Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits.

Reserved

PINCAP15

PINCAP14

PINCAP13

PINCAP12

PINCAP11

PINCAP10

PINCAP9

PINCAP8

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004)

Table 2-11. CFGPIN1 Register Bit Field Description (0x4000 0004)

BIT NO.

NAME

DESCRIPTION

31:8

Reserved

Reads are indeterminate. Only 0s should be written to these bits.

PINCAP15

AXR0[5]/SPI1_SCS pin state captured on rising edge of RESET pin.

PINCAP14

AXR0[6]/SPI1_ENA pin state captured on rising edge of RESET pin.

PINCAP13

UHPI_HCS pin state captured on rising edge of RESET pin.

PINCAP12

UHPI_HD[0] pin state captured on rising edge of RESET pin.

PINCAP11

EM_D[16]/UHPI_HA[0] pin state captured on rising edge of RESET pin.

PINCAP10

AFSX0 pin state captured on rising edge of RESET pin.

PINCAP9

AFSR0 pin state captured on rising edge of RESET pin.

PINCAP8

AXR0[0] pin state captured on rising edge of RESET pin.

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TMS320C6720RFP300 Datenblatt(PDF) 18 Page - Texas Instruments