TMS320C6720RFP300 datasheet(17/118 Pages) TI

17 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits.

Reserved

PINCAP7

PINCAP6

PINCAP5

PINCAP4

PINCAP3

PINCAP2

PINCAP1

PINCAP0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000)

Table 2-10. CFGPIN0 Register Bit Field Description (0x4000 0000)

BIT NO.

NAME

DESCRIPTION

31:8

Reserved

Reads are indeterminate. Only 0s should be written to these bits.

PINCAP7

SPI0_SOMI/I2C0_SDA pin state captured on rising edge of RESET pin.

PINCAP6

SPI0_SIMO pin state captured on rising edge of RESET pin.

PINCAP5

SPI0_CLK/I2C0_SCL pin state captured on rising edge of RESET pin.

PINCAP4

SPI0_SCS/I2C1_SCL pin state captured on rising edge of RESET pin.

PINCAP3

SPI0_ENA/I2C1_SDA pin state captured on rising edge of RESET pin.

PINCAP2

AXR0[8]/AXR1[5]/SPI1_SOMI pin state captured on rising edge of RESET pin.

PINCAP1

AXR0[9]/AXR1[4]/SPI1_SIMO pin state captured on rising edge of RESET pin.

PINCAP0

AXR0[7]/SPI1_CLK pin state captured on rising edge of RESET pin.

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TMS320C6720RFP300 Datenblatt(PDF) 17 Page - Texas Instruments