MCP3901 datasheet(31/60 Pages) MICROCHIP

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DS22192C-page 31

MCP3901

5.10.1

PHASE DELAY LIMITS

The phase delay can only go from -OSR/2 to

+OSR/2 – 1. This sets the fine phase resolution. The

PHASE register is coded with 2’s complement.

If larger delays between the two channels are needed,

they can be implemented externally to the chip with an

MCU. A FIFO in the MCU can save incoming data from

the leading channel for a number N of DRCLK clocks.

In this case, DRCLK would represent the coarse timing

resolution, and DMCLK, the fine timing resolution. The

total delay will then be equal to:

Delay = N/DRCLK + PHASE/DMCLK

The Phase Delay register can be programmed once

with the OSR = 256 setting and will adjust to the OSR

automatically afterwards, without the need to change

the value of the PHASE register.

• OSR = 256: The delay can go from -128 to +127.

PHASE<7> is the sign bit, PHASE<6> is the MSB

and PHASE<0> is the LSB.

• OSR = 128: The delay can go from -64 to +63.

PHASE<6> is the sign bit, PHASE<5> is the MSB

and PHASE<0> is the LSB.

• OSR = 64: The delay can go from -32 to +31.

PHASE<5> is the sign bit, PHASE<4> is the MSB

and PHASE<0> is the LSB.

• OSR = 32: The delay can go from -16 to +15.

PHASE<4> is the sign bit, PHASE<3> is the MSB

and PHASE<0> is the LSB.

5.11

Crystal Oscillator

The MCP3901 includes a Pierce type crystal oscillator

with very high stability and ensures very low tempera-

ture and jitter for the clock generation. This oscillator

can handle up to 16.384 MHz crystal frequencies pro-

vided that proper load capacitances and the quartz

quality factor are used.

For keeping specified ADC accuracy, AMCLK should

be kept between 1 and 5 MHz with BOOST off or 1 and

8.192 MHz with BOOST on. Larger MCLK frequencies

can be used provided the prescaler clock settings allow

the AMCLK to respect these ranges.

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND, and

between OSC2 and DGND. They should also respect

the following equation:

EQUATION 5-6:

When CLKEXT = 1, the crystal oscillator is bypassed

by a digital buffer to allow direct clock input for an

external clock (see Figure 1-5).

TABLE 5-8:

PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 256

PHASE

Hex

Delay

(CH0 relative

to CH1)

01 11 111 1

0x7F

+127 µs

01 11 111 0

0x7E

+126 µs

00 00 000 1

0x01

+1 µs

00 00 000 0

0x00

0 µs

11 11 111 1

0xFF

-1 µs

10 00 000 1

0x81

-127 µs

10 00 000 0

0x80

-128 µs

1.6

LOAD

-----------------

⎝⎠

⎛⎞

Where:

Crystal frequency in MHz

CLOAD

Load capacitance in pF including

parasitics from the PCB

Motional resistance in ohms of

the quartz

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