MCP3901 datasheet(33/60 Pages) MICROCHIP

33 / 60 page

DS22192C-page 33

MCP3901

6.0

SERIAL INTERFACE

DESCRIPTION

6.1

Overview

The MCP3901 device is compatible with SPI Modes 0,0

and 1,1. Data is clocked out of the MCP3901 on the

falling edge of SCK and data is clocked into the

MCP3901 on the rising edge of SCK. In these modes,

SCK can Idle either high or low.

Each SPI communication starts with a CS falling edge

and stops with the CS rising edge. Each SPI

communication is independent. When CS is high, SDO

is in high-impedance, and transitions on SCK and SDI

have no effect. Additional controls: RESET, DR and

MDAT0/1 are also provided on separate pins for

advanced communication.

The MCP3901 interface has a simple command

structure. The first byte transmitted is always the

CONTROL byte and is followed by data bytes that are

8-bit wide. Both ADCs are continuously converting data

by default and can be reset or shut down through a

CONFIG2 register setting.

Since each ADC data is either 16 or 24 bits (depending

on the WIDTH bits), the internal registers can be

grouped together with various configurations (through

the READ bits) in order to allow easy data retrieval within

only one communication. For device reads, the internal

address counter can be automatically incremented in

order to loop through groups of data within the register

map. The SDO will then output the data located at the

ADDRESS (A<4:0>) defined in the control byte and then

ADDRESS + 1 depending on the READ<1:0> bits,

which select the groups of registers. These groups are

defined in Section 7.1 “ADC Channel Data Output

Registers” (Register Map).

The Data Ready pin (DR) can be used as an interrupt

for an MCU and outputs pulses when new ADC chan-

nel data is available. The RESET pin acts like a Hard

Reset and can reset the part to its default power-up

configuration. The MDAT0/1 pins give the modulator

outputs (see Section 5.4 “Modulator Output Block”).

6.2

Control Byte

The control byte of the MCP3901 contains two device

Address bits, A<6:5>, 5 register Address bits, A<4:0>,

and a Read/Write bit (R/W). The first byte transmitted

to the MCP3901 is always the control byte.

The

MCP3901

interface

device

addressable

(through A<6:5>) so that multiple MCP3901 chips can

be present on the same SPI bus with no data bus

contention. This functionality enables three-phase

power metering systems, containing three MCP3901

chips, controlled by a single SPI bus (single CS, SCK,

SDI and SDO pins).

FIGURE 6-1:

Control Byte.

The default device address bits are ‘00’. Contact the

Microchip factory for additional device address bits. For

more information, please see the Product Identification

System.

A read on undefined addresses will give an all zeros

output on the first, and all subsequent transmitted

bytes. A write on an undefined address will have no

effect and also, will not increment the address counter.

The register map is defined in Section 7.1 “ADC

Channel Data Output Registers”.

6.3

Reading from the Device

The first data byte read is the one defined by the

address given in the CONTROL byte. After this first

byte is transmitted, if the CS pin is maintained low, the

communication continues and the address of the next

transmitted byte is determined by the status of the

READ bits in the STATUS/COM register. Multiple

looping configurations can be defined through the

READ<1:0> bits for the address increment (see

Section 6.6 “SPI MODE 0,0 – Clock Idle Low, Read/

Write Examples”).

6.4

Writing to the Device

The first data byte written is the one defined by the

address

given

the

control

byte.

The

write

communication automatically increments the address

for subsequent bytes.

The address of the next transmitted byte within the

same communication (CS stays low) is the next

address defined on the register map. At the end of the

effect.

The SDO pin stays in high-impedance during a write

communication.

6.5

SPI MODE 1,1 – Clock Idle High,

Read/Write Examples

In this SPI mode, the clock Idles high. For the

MCP3901, this means that there will be a falling edge

before there is a rising edge.

Note:

Changing from an SPI Mode 1,1 to an SPI

Mode 0,0 is possible, but needs a Reset

pulse

in-between

ensure

correct

communication.

R/W

Read/

Write Bit

Device

Address Bits

Address

Bits

MCP3901 Datenblatt(PDF) 33 Page - Microchip Technology

MCP3901 Datenblatt(HTML) 33 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datenblatt Download

Link URL