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MMA8451 Datenblatt(PDF) 24 Page - Freescale Semiconductor, Inc

Teilenummer MMA8451
Bauteilbeschribung  3-Axis, 12-bit/8-bit Digital Accelerometer
PDF  47 Pages
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Hersteller  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MMA8451 Datenblatt(HTML) 24 Page - Freescale Semiconductor, Inc

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MMA8452Q
Sensors
24
Freescale Semiconductor, Inc.
0x11: Portrait/Landscape Configuration Register
This register enables the Portrait/Landscape function and sets the behavior of the debounce counter.
0x12: Portrait/Landscape Debounce Counter
This register sets the debounce count for the orientation state transition. The minimum debounce latency is determined by the
data rate set by the product of the selected system ODR and PL_COUNT registers. Any transition from WAKE to SLEEP or vice
versa resets the internal Landscape/Portrait debounce counter. Note: The debounce counter weighting (time step) changes
based on the ODR and the Oversampling mode. Table 22 explains the time step value for all sample rates and all Oversampling
modes.
0x13: PL_BF_ZCOMP Back/Front and Z Compensation Register
The Z-Lock angle compensation is set to 29°. The Back to Front trip angle is set to ±75°.
Note: All angles are accurate to ±2°.
0x11: PL_CFG Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBCNTM
PL_EN
0
0
0
0
0
0
Table 20. PL_CFG Description
DBCNTM
Debounce counter mode selection. Default value: 1
0: Decrements debounce whenever condition of interest is no longer valid.
1: Clears counter whenever condition of interest is no longer valid.
PL_EN
Portrait/Landscape Detection Enable. Default value: 0
0: Portrait/Landscape Detection is Disabled.
1: Portrait/Landscape Detection is Enabled.
0x12: PL_COUNT Register (Read/Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBNCE[7]
DBNCE[6]
DBNCE[5]
DBNCE[4]
DBNCE[3]
DBNCE[2]
DBNCE[1]
DBNCE[0]
Table 21. PL_COUNT Description
DBCNE[7:0]
Debounce Count value. Default value: 0000_0000.
Table 22. PL_COUNT Relationship with the ODR
ODR (Hz)
Max Time Range (s)
Time Step (ms)
Normal
LPLN
HighRes
LP
Normal
LPLN
HighRes
LP
800
0.319
0.319
0.319
0.319
1.25
1.25
1.25
1.25
400
0.638
0.638
0.638
0.638
2.5
2.5
2.5
2.5
200
1.28
1.28
0.638
1.28
5
5
2.5
5
100
2.55
2.55
0.638
2.55
10
10
2.5
10
50
5.1
5.1
0.638
5.1
20
20
2.5
20
12.5
5.1
20.4
0.638
20.4
20
80
2.5
80
6.25
5.1
20.4
0.638
40.8
20
80
2.5
160
1.56
5.1
20.4
0.638
40.8
20
80
2.5
160
0x13: PL_BF_ZCOMP Register (Read Only)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BKFR[1]
BKFR[0]
0
0
0
ZLOCK[2]
ZLOCK[1]
ZLOCK[0]
Table 23. PL_BF_ZCOMP Description
BKFR[1:0]
Back Front Trip Angle Fixed Threshold = 01 which is
≥ ±75°.
ZLOCK[2:0]
Z-Lock Angle Fixed Threshold = 100 which is 29°.



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