MMA8452Q

Sensors

36

Freescale Semiconductor, Inc.

6.6

Auto-WAKE/SLEEP Detection

The ASLP_COUNT register sets the minimum time period of inactivity required to change current ODR value from the value

specified in the DR[2:0] register to ASLP_RATE register value, provided the SLPE bit is set to a logic ‘1’ in the CTRL_REG2

register. See Table 52 for functional blocks that may be monitored for inactivity in order to trigger the “return to SLEEP” event.

D7-D0 defines the minimum duration time to change current ODR value from DR to ASLP_RATE. Time step and maximum

value depend on the ODR chosen as shown in Table 51.

In order to wake the device, the desired function or functions must be enabled in CTRL_REG4 and set to WAKE to SLEEP in

CTRL_REG3. All enabled functions will still function in SLEEP mode at the SLEEP ODR. Only the functions that have been

selected for WAKE from SLEEP will WAKE the device.

MMA8452Q has 4 functions that can be used to keep the sensor from falling asleep namely, Transient, Orientation, Pulse, and

Motion/FF. One or more of these functions can be enabled. In order to WAKE the device, 4 functions are provided namely,

Transient, Orientation, Pulse, and the Motion/Freefall. The Auto-WAKE/SLEEP interrupt does not affect the WAKE/SLEEP, nor

does the data ready interrupt. See Register 0x2C for the WAKE from SLEEP bits.

If the Auto-SLEEP bit is disabled, then the device can only toggle between STANDBY and WAKE mode. If Auto-SLEEP

interrupt is enabled, transitioning from ACTIVE mode to Auto-SLEEP mode and vice versa generates an interrupt.

0x29: ASLP_COUNT Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D7

D6

D5

D4

D3

D2

D1

D0

Table 50. ASLP_COUNT Description

D[7:0]

Duration value. Default value: 0000_0000.

Table 51. ASLP_COUNT Relationship with ODR

Output Data Rate

(ODR)

Duration

ODR Time Step

ASLP_COUNT Step

800 Hz

0 to 81s

1.25 ms

320 ms

400 Hz

0 to 81s

2.5 ms

320 ms

200 Hz

0 to 81s

5 ms

320 ms

100 Hz

0 to 81s

10 ms

320 ms

50 Hz

0 to 81s

20 ms

320 ms

12.5 Hz

0 to 81s

80 ms

320 ms

6.25 Hz

0 to 81s

160 ms

320 ms

1.56 Hz

0 to 162s

640 ms

640 ms

Table 52. SLEEP/WAKE Mode Gates and Triggers

Interrupt Source

Event restarts timer and

delays Return to SLEEP

Event will WAKE from SLEEP

SRC_TRANS

Yes

Yes

SRC_LNDPRT

Yes

Yes

SRC_PULSE

Yes

Yes

SRC_FF_MT

Yes

Yes

SRC_ASLP

No*

No*

SRC_DRDY

No

No