MMA8452Q

Sensors

40

Freescale Semiconductor, Inc.

0x2E: CTRL_REG5 Register (Read/Write)

The system’s interrupt controller shown in Figure 10 uses the corresponding bit field in the CTRL_REG5 register to determine

the routing table for the INT1 and INT2 interrupt pins. If the bit value is logic ‘0’ the functional block’s interrupt is routed to INT2,

and if the bit value is logic ‘1’ then the interrupt is routed to INT1. One or more functions can assert an interrupt pin; therefore a

host application responding to an interrupt should read the INT_SOURCE (0x0C) register to determine the appropriate sources

of the interrupt.

6.8

User Offset Correction Registers

For more information on how to calibrate the 0g Offset refer to AN4069 Offset Calibration Using the MMA8452Q. The 2’s

complement offset correction registers values are used to realign the Zero-g position of the X, Y, and Z-axis after device board

mount. The resolution of the offset registers is 2 mg per LSB. The 2’s complement 8-bit value would result in an offset

compensation range ±256 mg.

0x2F: OFF_X Offset Correction X Register

0x30: OFF_Y Offset Correction Y Register

0x31: OFF_Z Offset Correction Z Register

0x2E: CTRL_REG5 Interrupt Configuration Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INT_CFG_ASLP

0

INT_CFG_TRANS INT_CFG_LNDPRT INT_CFG_PULSE

INT_CFG_FF_MT

0

INT_CFG_DRDY

Table 62. Interrupt Configuration Register Description

Interrupt Configuration

Description

INT_CFG_ASLP

INT1/INT2 Configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_TRANS

INT1/INT2 Configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_LNDPRT

INT1/INT2 Configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_PULSE

INT1/INT2 Configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_FF_MT

INT1/INT2 Configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

INT_CFG_DRDY

INT1/INT2 Configuration. Default value: 0.

0: Interrupt is routed to INT2 pin; 1: Interrupt is routed to INT1 pin

0x2F: OFF_X Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D7

D6

D5

D4

D3

D2

D1

D0

Table 63. OFF_X Description

D[7:0]

X-axis offset value. Default value: 0000_0000.

0x30: OFF_Y Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D7

D6

D5

D4

D3

D2

D1

D0

Table 64. OFF_Y Description

D[7:0]

Y-axis offset value. Default value: 0000_0000.

0x31: OFF_Z Register (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D7

D6

D5

D4

D3

D2

D1

D0

Table 65. OFF_Z Description

D[7:0]

Z-axis offset value. Default value: 0000_0000.