PCAL9554CBS datasheet(19/42 Pages) NXP

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PCAL9554B_PCAL9554C

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Product data sheet

Rev. 2 — 10 December 2012

19 of 42

NXP Semiconductors

PCAL9554B; PCAL9554C

Low-voltage 8-bit I2C-bus/SMBus low power I/O port

[1]

Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD <1 s.

[2]

Glitch width that will not cause a functional disruption when

V

DD(gl) =0.5  VDD.

Glitches in the power supply can also affect the power-on reset performance of this

device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each

other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 19 and Table 18 provide more information on

how to measure these specifications.

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition

is released and all the registers and the I2C-bus/SMBus state machine are initialized to

their default states. The value of VPOR differs based on the VDD being lowered to or from

0V. Figure 20 and Table 18 provide more details on this specification.

Table 18.

Recommended supply sequencing and ramp rates

Tamb =25 C (unless otherwise noted). Not tested; specified by design.

Symbol

Parameter

Condition

Min

Typ

Max

Unit

(dV/dt)f

fall rate of change of voltage

Figure 17

0.1

2000

(dV/dt)r

rise rate of change of voltage

Figure 17

0.1

2000

td(rst)

reset delay time

Figure 17; re-ramp time when

VDD drops to VSS

s

Figure 18; re-ramp time when

VDD drops to VPOR(min)  50 mV

s

V

DD(gl)

glitch supply voltage difference

Figure 19

[1] --1.0

tw(gl)VDD

supply voltage glitch pulse width

Figure 19

[2] --10

s

VPOR(trip)

power-on reset trip voltage

falling VDD

0.7

--V

rising VDD

--1.4

Fig 19. Glitch width and glitch height

Fig 20. Power-on reset voltage (VPOR)

002aah331

VDD

time

tw(gl)VDD

∆VDD(gl)

002aah332

POR

time

VDD

time

VPOR (rising VDD)

VPOR (falling VDD)

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