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PCAL9554CBS Datenblatt(PDF) 10 Page - NXP Semiconductors

Teilenummer PCAL9554CBS
Bauteilbeschribung  Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O
PDF  42 Pages
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
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PCAL9554CBS Datenblatt(HTML) 10 Page - NXP Semiconductors

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PCAL9554B_PCAL9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
10 of 42
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
6.4.11 Output port configuration register (47h)
The output port configuration register selects port-wise push-pull or open-drain I/O stage.
A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 6). A logic 1
configures the I/O as open-drain (Q1 is disabled, Q2 is active).
6.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
Table 17.
Output port configuration register (address 47h)
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
ODEN0
Default
00
00
00
00
On power-up or reset, all registers return to default values.
Fig 6.
Simplified schematic of the I/Os (P0 to P7)
INTERRUPT
MASK
VDD
P0 to P7
output port
register data
configuration
register
DQ
CK
Q
data from
shift register
write
configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
002aah101
FF
data from
shift register
FF
FF
FF
Q1
Q2
VSS
to INT
PULL-UP/PULL-DOWN
CONTROL
ESD
protection
diode
100 kΩ
VDD
ESD
protection
diode
input port
latch
DQ
EN
LATCH
read pulse
input latch
register
DQ
CK
FF
data from
shift register
write input
latch pulse



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