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PCAL9554CBS Datenblatt(PDF) 28 Page - NXP Semiconductors

Teilenummer PCAL9554CBS
Bauteilbeschribung  Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O
PDF  42 Pages
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Hersteller  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
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PCAL9554CBS Datenblatt(HTML) 28 Page - NXP Semiconductors

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PCAL9554B_PCAL9554C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 10 December 2012
28 of 42
NXP Semiconductors
PCAL9554B; PCAL9554C
Low-voltage 8-bit I2C-bus/SMBus low power I/O port
13. Dynamic characteristics
Table 23.
I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
kHz
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tSP
pulse width of spikes that must
be suppressed by the input filter
050
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20
(VDD /5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4
-
0.6
-
s
tVD;DAT
data valid time
SCL LOW to
SDA output valid
-3.45
-
0.9
s
tVD;ACK
data valid acknowledge time
ACK signal
from SCL LOW
to SDA (out) LOW
-3.45
-
0.9
s
Table 24.
Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 29.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
tv(INT)
valid time on pin INT
from P port to INT
-1-
1
s
trst(INT)
reset time on pin INT
from SCL to INT
-1-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns



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