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PCAL9554CBS Datenblatt(PDF) 6 Page - NXP Semiconductors |
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PCAL9554CBS Datenblatt(HTML) 6 Page - NXP Semiconductors |
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6 / 42 page ![]() PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 2 — 10 December 2012 6 of 42 NXP Semiconductors PCAL9554B; PCAL9554C Low-voltage 8-bit I2C-bus/SMBus low power I/O port [1] Undefined. 6.3 Interface definition 6.4 Register descriptions 6.4.1 Input port register (00h) The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port register is read only; writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is performed as described in Section 7.2 “Read commands”. 6.4.2 Output port register (01h) The Output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from this register reflect the value that was written to this register, not the actual pin value. Table 4. Command byte Pointer register bits Command byte (hexadecimal) Register Protocol Power-up default B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 00h Input port read byte xxxx xxxx[1] 0 0 0 0 0 0 0 1 01h Output port read/write byte 1111 1111 0 0 0 0 0 0 1 0 02h Polarity Inversion read/write byte 0000 0000 0 0 0 0 0 0 1 1 03h Configuration read/write byte 1111 1111 0 1 0 0 0 0 0 0 40h Output drive strength 0 read/write byte 1111 1111 0 1 0 0 0 0 0 1 41h Output drive strength 1 read/write byte 1111 1111 0 1 0 0 0 0 1 0 42h Input latch read/write byte 0000 0000 0 1 0 0 0 0 1 1 43h Pull-up/pull-down enable read/write byte 0000 0000 0 1 0 0 0 1 0 0 44h Pull-up/pull-down selection read/write byte 1111 1111 0 1 0 0 0 1 0 1 45h Interrupt mask read/write byte 1111 1111 0 1 0 0 0 1 1 0 46h Interrupt status read byte 0000 0000 0 1 0 0 0 1 1 1 47h Output port configuration read/write byte 0000 0000 Table 5. Interface definition Byte Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C-bus slave address L H L/H L/H A2 A1 A0 R/W I/O data bus P7 P6 P5 P4 P3 P2 P1 P0 Table 6. Input port register (address 00h) Bit 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 Default XX XX XX XX |
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