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WM8952ECS/RV Datenblatt(PDF) 45 Page - Wolfson Microelectronics plc |
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WM8952ECS/RV Datenblatt(HTML) 45 Page - Wolfson Microelectronics plc |
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45 / 72 page ![]() Pre Production WM8952 w PP, Rev 3.1, June 2011 45 The PLL frequency ratio R = f2/f1 (see Table 33) can be set using the register bits PLLK and PLLN: N = int R K = int (224 (R - N)) N controls the ratio of the division, and K the fractional part. The PLL output then passes through a fixed divide by 4, and can also be further divided by MCLKDIV[3:0] (see Figure 24). The divided clock (SYSCLK) can be used to clock the WM8952 DSP core. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R36 PLL N value 7 PLL_POWERDOWN 0 PLL POWER 0=ON 1=OFF 6 FRACEN 1 Fractional Divide within the PLL 0=Disabled (Lower Power) 1=Enabled 5:4 PLLPRESCALE 00 00 = MCLK input multiplied by 2 (default) 01 = MCLK input not divided 10 = Divide MCLK by 2 before input to PLL 11 = Divide MCLK by 4 before input to PLL 3:0 PLLN 1000 Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. R37 PLL K value 1 5:0 PLLK [23:18] 0Ch Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). R38 PLL K Value 2 8:0 PLLK [17:9] 093h R39 PLL K Value 3 8:0 PLLK [8:0] 0E9h Table 33 PLL Frequency Ratio Control INTEGER N DIVISION The integer division ratio (N) is determined by N[3:0] and must be in the range 5 to 12 . If the PLL frequency is an exact integer (5,6,7,8,9,10,11,12) then FRAC_EN can be set to 0 for low power operation. INPUT CLOCK (F1) DESIRED PLL OUTPUT (F2) DIVISION REQUIRED (R) FRACTIONAL DIVISION (K) INTEGER DIVISION (N) SDM 11.2896MHz 90.3168MHz 8 0 8 0 12.2880MHz 98.3040MHz 8 0 8 0 Table 34 PLL Modes of Operation (Integer N mode) FRACTIONAL K MODE The Fractional K bits provides K[23:0] provide finer divide resolution for the PLL frequency ratio (up to 1/224). If these are used then FRAC_EN must be set. The relationship between the required division X, the fractional division K[23:0] and the integer division N[3:0] is: K = 224 ( R – N) where 0 < (R – N) < 1 and K is rounded to the nearest whole number. |
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