WM8952ECSSLASHRV datasheet(62/72 Pages) WOLFSON

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WM8952

Pre Production

PP, Rev 3.1, June 2011

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

32 (20h)

15:10 ALCGAIN[5:0]

000000

Readback from this register will return the ALC gain in

this position

Input Limiter /

Automatic Level

Control (ALC)

Reserved

ALCSEL

ALC function select

0=ALC disabled

1=ALC enabled

Input Limiter /

Automatic Level

Control (ALC)

7:6

Reserved

5:3

ALCMAX

111

Set Maximum Gain of PGA

Input Limiter /

Automatic Level

Control (ALC)

2:0

ALCMIN

000

Set minimum gain of PGA

Input Limiter /

Automatic Level

Control (ALC)

33 (21h)

15:8

000h

Reserved

7:4

ALCHLD

000

ALC hold time before gain is increased.

Input Limiter /

Automatic Level

Control (ALC)

3:0

ALCLVL

1011

ALC threshold level. Sets the desired signal level.

Input Limiter /

Automatic Level

Control (ALC)

34 (22h)

15:9

00h

Reserved

ALCMODE

Determines the ALC mode of operation:

0=Normal mode

1=Limiter mode.

Input Limiter /

Automatic Level

Control (ALC)

7:4

ALCDCY

0011

Decay (gain ramp-up) time

Input Limiter /

Automatic Level

Control (ALC)

3:0

ALCATK

0010

ALC attack (gain ramp-down) time

Input Limiter /

Automatic Level

Control (ALC)

35 (23h)

15:4

000h

Reserved

NGEN

Noise gate function enable

1 = enable

0 = disable

Input Limiter /

Automatic Level

Control (ALC)

2:0

NGTH

000

Noise gate threshold

Input Limiter /

Automatic Level

Control (ALC)

36 (24h)

15:8

00h

Reserved

PLL_POWERD

OWN

PLL POWER

0=On

1=Off

Master Clock and

Phase Locked

Loop (PLL)

FRACEN

Fractional Divide within the PLL

0=Disabled (Lower Power)

1=Enabled

Master Clock and

Phase Locked

Loop (PLL)

5:4

PLLPRESCALE 00

00 = MCLK input multiplied by 2 (default)

01 = MCLK input not divided

10 = Divide MCLK by 2 before input to PLL

11 = Divide MCLK by 4 before input to PLL

Master Clock and

Phase Locked

Loop (PLL)

3:0

PLLN[3:0]

1100

Integer (N) part of PLL input/output frequency ratio.

Use values greater than 5 and less than 13.

Master Clock and

Phase Locked

Loop (PLL)

37 (25h)

15:6

000h

Reserved

5:0

PLLK[23:18]

001100

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

38 (26h)

15:9

00h

Reserved

WM8952ECS/RV Datenblatt(PDF) 62 Page - Wolfson Microelectronics plc

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