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WM8952ECS/RV Datenblatt(PDF) 59 Page - Wolfson Microelectronics plc

Teilenummer WM8952ECS/RV
Bauteilbeschribung  Mono ADC with Microphone Pre-amplifier
PDF  72 Pages
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Hersteller  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8952ECS/RV Datenblatt(HTML) 59 Page - Wolfson Microelectronics plc

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Pre Production
WM8952
w
PP, Rev 3.1, June 2011
59
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
4:2
BCLKDIV
000
Configures the BCLK and FRAME output frequency,
for use when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Digital Audio
Interfaces
1
0
Reserved
0
MS
0
Sets the chip to be master over FRAME and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs generated by
the WM8952 (MASTER)
Digital Audio
Interfaces
7 (07h)
15:6
00000
Reserved
6
Reserved
5
SOFT_START
0
VMID Soft Start
0=disabled
1=enabled
POP Minimisation
4
TOGGLE
0
Fast VMID Discharge
0=normal
1=enable (used during power-down)
POP Minimisation
3:1
SR
000
Approximate sample rate (configures the coefficients
for the internal digital filters):
000=48kHz
001=32kHz
010=24kHz
011=16kHz
100=12kHz
101=8kHz
110-111=reserved
Audio Sample
Rates
0
SLOWCLKEN
0
Enables the Timeout Clock for zero cross detection.
Zero Cross
Timeout
8 (08h)
15:8
00h
Reserved
7
MODE_GPIO
0
Selects MODE as a GPIO pin
0 = MODE is an input. MODE selects 2-wire mode
when low and 3-wire mode when high.
1 = MODE can be an input or output under the control
of the GPIO control register. Interface operates in 3-
wire mode regardless of when happens on the MODE
pin.
Control Interface
6
0
Reserved
5:4
OPCLKDIV
00
PLL Output clock division ratio
00=divide by 1
01=divide by 2
10=divide by 3
11=divide by 4
General Purpose
Input Output
3
GPIOPOL
0
GPIO Polarity invert
0=Non inverted
1=Inverted
General Purpose
Input Output



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