AD9517-1ASLASHPCBZ datasheet(74/80 Pages) AD

74 / 80 page

AD9517-1

Data Sheet

Rev. E | Page 74 of 80

Reg.

Addr.

(Hex)

Bits

Name

Description

0x19F

[7:4]

Phase Offset Divider 3.2

Refer to LVDS/CMOS channel divider function description (default = 0x0).

[3:0]

Phase Offset Divider 3.1

Refer to LVDS/CMOS channel divider function description (default = 0x0).

0x1A0

[7:4]

Low Cycles Divider 3.2

Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0]

High Cycles Divider 3.2

Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x1A1

Bypass Divider 3.2

Bypasses (and powers down) 3.2 divider logic; routes clock to 3.2 output.

0: does not bypass (default).

1: bypasses.

Bypass Divider 3.1

Bypasses (and powers down) 3.1 divider logic; routes clock to 3.1 output.

0: does not bypass (default).

1: bypasses.

Divider 3 nosync

Nosync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Divider 3 force high

Forces Divider 3 output high. Requires that nosync also be set.

0: forces low (default).

1: forces high.

Start High Divider 3.2

Divider 3.2 start high/low.

0: starts low (default).

1: starts high.

Start High Divider 3.1

Divider 3.1 start high/low.

0: starts low (default).

1: starts high.

0x1A2

Divider 3 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

AD9517-1A/PCBZ Datenblatt(PDF) 74 Page - Analog Devices

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