AD9517-1ASLASHPCBZ datasheet(75/80 Pages) AD

75 / 80 page

Data Sheet

AD9517-1

Rev. E | Page 75 of 80

Table 60. VCO Divider and CLK Input

Reg.

Addr

(Hex)

Bits

Name

Description

0x1E0

[2:0]

VCO divider

Divide

4 (default).

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

0x1E1

Power down clock input section

Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).

0: normal operation (default).

1: power-down.

Power down VCO clock interface

Powers down the interface block between VCO and clock distribution.

0: normal operation (default).

1: power-down.

Power down VCO and CLK

Powers down both VCO and CLK input.

0; normal operation (default).

1: power-down.

Select VCO or CLK

Selects either the VCO or the CLK as the input to VCO divider.

0: selects external CLK as input to VCO divider (default).

1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.

Bypass VCO divider

Bypasses or uses the VCO divider.

0: uses VCO divider (default).

1: bypasses VCO divider; cannot select VCO as input when this is selected.

Table 61. System

Reg.

Addr.

(Hex)

Bits

Name

Description

0x230

Power down sync

Powers down the sync function.

0: normal operation of the sync function (default).

1: powers down sync circuitry.

Power down distribution reference

Powers down the reference for distribution section.

0: normal operation of the reference for the distribution section (default).

1: powers down the reference for the distribution section.

Soft sync

The soft sync bit works the same as the SYNC pin, except that the polarity of the bit

is reversed. That is, a high level forces selected channels into a predetermined static

state, and a 1-to-0 transition triggers a sync.

0: same as SYNC high (default).

1: same as SYNC low.

Table 62. Update All Registers

Reg.

Addr

(Hex)

Bits

Name

Description

0x232

Update all registers

This bit must be set to 1b to transfer the contents of the buffer registers into the active

registers. This bit is self-clearing; that is, it does not have to be set back to 0b.

1 (self-clearing): updates all active registers to the contents of the buffer registers.

AD9517-1A/PCBZ Datenblatt(PDF) 75 Page - Analog Devices

AD9517-1A/PCBZ Datenblatt(HTML) 75 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datenblatt Download

Link URL