AD9517-1ASLASHPCBZ datasheet(77/80 Pages) AD

77 / 80 page

Data Sheet

AD9517-1

Rev. E | Page 77 of 80

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9517 provide the lowest jitter

clock signals that are available from the AD9517. The LVPECL

outputs (because they are open emitter) require a dc termination

to bias the output transistors. The simplified equivalent circuit in

Figure 59 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin termination

(see Figure 71) or Y-termination (see Figure 72) is recommended.

In each case, the VS of the receiving buffer should match the

VS_LVPECL voltage. If it does not, ac coupling is recommended (see

Figure 73). In the case of Figure 73, pull-down resistors of <150 Ω

are not recommended when VS_LVEPCL = 3.3 V; if used, damage to

the LVPECL drivers may result. The minimum recommended

pull-down resistor size for VS_LVPECL = 2.5 V is 100 Ω.

The resistor network is designed to match the transmission line

impedance (50 Ω) and the switching threshold (VS − 1.3 V).

VS_LVPECL

LVPECL

50Ω

SINGLE-ENDED

(NOT COUPLED)

VS_DRV

LVPECL

127Ω

83Ω

Figure 71. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination

VS_LVPECL

LVPECL

Z0 = 50Ω

VS = 3.3V

LVPECL

50Ω

Z0 = 50Ω

Figure 72. DC-Coupled 3.3 V LVPECL Y-Termination

VS_LVPECL

LVPECL

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

LVPECL

100Ω

0.1nF

200Ω

Figure 73. AC-Coupled LVPECL with Parallel Transmission Line

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue. In the case

shown in Figure 72, where VS_LVPECL = 2.5 V, the 50 Ω

termination resistor that is connected to ground should be

changed to 19 Ω.

Thevenin-equivalent termination uses a resistor network to

provide 50 Ω termination to a dc voltage that is below VOL of

the LVPECL driver. In this case, VS_LVPECL on the AD9517

should equal VS of the receiving buffer. Although the resistor

combination shown in Figure 72 results in a dc bias point of

VS_LVPECL − 2 V, the actual common-mode voltage is

VS_LVPECL − 1.3 V because additional current flows from the

AD9517 LVPECL driver through the pull-down resistor.

The circuit is identical when VS_LVPECL = 2.5 V, except that the

pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.

LVDS CLOCK DISTRIBUTION

The AD9517 provides four clock outputs (OUT4 to OUT7) that

are selectable as either CMOS or LVDS level outputs. LVDS is a

differential output option that uses a current mode output stage.

The nominal current is 3.5 mA, which yields 350 mV output swing

across a 100 Ω resistor. An output current of 7 mA is also available

in cases where a larger output swing is required. The LVDS

output meets or exceeds all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is

shown in Figure 74.

LVDS

100Ω

DIFFERENTIAL (COUPLED)

LVDS

100Ω

Figure 74. LVDS Output Termination

See the AN-586 Application Note, LVDS Data Outputs for High-

Speed Analog-to-Digital Converters for more information on LVDS.

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