AD9517-0ASLASHPCBZ datasheet(32/80 Pages) AD

32 / 80 page

AD9517-0

Data Sheet

Rev. E | Page 32 of 80

Clock Distribution or External VCO < 1600 MHz

When the external clock source to be distributed or the external

VCO/VCXO is less than 1600 MHz, a configuration that bypasses

the VCO divider can be used. This configuration differs from

the High Frequency Clock Distribution—CLK or External VCO

> 1600 MHz section only in that the VCO divider (divide-by-2,

divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.

This limits the frequency of the clock source to <1600 MHz (due

to the maximum input frequency allowed at the channel dividers).

Configuration and Register Settings

For clock distribution applications where the external clock is

<1600 MHz, use the register settings that are shown in Table 25.

Table 25. Settings for Clock Distribution < 1600 MHz

Function

0x010[1:0] = 01b

PLL asynchronous power-down (PLL off)

0x1E1[0] = 1b

Bypass the VCO divider as source for

distribution section

0x1E1[1] = 0b

CLK selected as the source

When using the internal PLL with an external VCO of <1600 MHz,

the PLL must be turned on.

Table 26. Settings for Using Internal PLL with External VCO <

1600 MHz

Function

0x1E1[0] = 1b

Bypass the VCO divider as source for

distribution section

0x010[1:0] = 00b

PLL normal operation (PLL on), along with

other appropriate PLL settings in Register 0x010

to Register 0x01D

An external VCO/VCXO requires an external loop filter that

must be connected between CP and the tuning pin of the

VCO/VCXO. This loop filter determines the loop bandwidth

and stability of the PLL. Make sure to select the proper PFD

polarity for the VCO/VCXO being used.

Table 27. Setting the PFD Polarity

Function

0x010[7] = 0b

PFD polarity positive (higher control voltage

produces higher frequency)

0x010[7] = 1b

PFD polarity negative (higher control voltage

produces lower frequency)

After the appropriate register values are programmed,

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