AD9517-0ASLASHPCBZ datasheet(2/80 Pages) AD

2 / 80 page

AD9517-0

Data Sheet

Rev. E | Page 2 of 80

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Power Supply Requirements ....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs .................................................................................. 6

Clock Outputs............................................................................... 6

Timing Characteristics ................................................................ 8

Clock Output Additive Phase Noise (Distribution Only;

VCO Divider Not Used).............................................................. 9

Clock Output Absolute Phase Noise (Internal VCO Used).. 10

Clock Output Absolute Time Jitter (Clock Generation

Using Internal VCO).................................................................. 11

Clock Output Absolute Time Jitter (Clock Cleanup

Using Internal VCO).................................................................. 11

Clock Output Absolute Time Jitter (Clock Generation

Using External VCXO) .............................................................. 11

Clock Output Additive Time Jitter (VCO Divider

Not Used)..................................................................................... 12

Clock Output Additive Time Jitter (VCO Divider Used) ..... 12

Delay Block Additive Time Jitter.............................................. 13

Serial Control Port ..................................................................... 13

PD, SYNC, and RESET Pins ..................................................... 14

LD, STATUS, and REFMON Pins............................................ 14

Power Dissipation....................................................................... 15

Timing Diagrams............................................................................ 16

Absolute Maximum Ratings.......................................................... 17

Thermal Resistance .................................................................... 17

ESD Caution................................................................................ 17

Pin Configuration and Function Descriptions........................... 18

Typical Performance Characteristics ........................................... 20

Terminology.................................................................................... 26

Detailed Block Diagram ................................................................ 27

Theory of Operation ...................................................................... 28

Operational Configurations...................................................... 28

Digital Lock Detect (DLD) ....................................................... 37

Clock Distribution ..................................................................... 41

Reset Modes ................................................................................ 49

Power-Down Modes .................................................................. 50

Serial Control Port ......................................................................... 51

Serial Control Port Pin Descriptions....................................... 51

General Operation of Serial Control Port............................... 51

The Instruction Word (16 Bits)................................................ 52

MSB/LSB First Transfers ........................................................... 52

Thermal Performance.................................................................... 55

Control Registers ............................................................................ 56

Control Register Map Overview .............................................. 56

Control Register Map Descriptions ......................................... 59

Applications Information .............................................................. 76

Frequency Planning Using the AD9517.................................. 76

Using the AD9517 Outputs for ADC Clock Applications.... 76

LVPECL Clock Distribution..................................................... 77

LVDS Clock Distribution.......................................................... 77

CMOS Clock Distribution ........................................................ 78

Outline Dimensions....................................................................... 79

Ordering Guide .......................................................................... 79

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