AD9517-0ASLASHPCBZ datasheet(47/80 Pages) AD

47 / 80 page

Data Sheet

AD9517-0

Rev. E | Page 47 of 80

Calculating the Fine Delay

The following values and equations are used to calculate the

delay of the delay block.

IRAMP (µA) = 200 × (Ramp Current + 1)

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;

001 = 2 + 1 = 3; 111 = 0 + 1 = 1.

Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286

( )

(

)

1600

0.34













−

RAMP

Caps

No.

Offset

Delay Full Scale (ns) = Delay Range + Offset

Fine Delay (ns) =

Delay Range × Delay Fraction × (1/63) + Offset

Note that only delay fraction values up to 47 decimal (101111b;

0x2F) are supported.

In no case can the fine delay exceed one-half of the output clock

period. If a delay longer than half of the clock period is attempted,

the output stops clocking.

The delay function adds some jitter that is greater than that

specified for the nondelayed output. This means that the delay

function should be used primarily for clocking digital chips,

such as FPGA, ASIC, DUC, and DDC. An output with this delay

enabled may not be suitable for clocking data converters. The

jitter is higher for long full scales because the delay block uses a

ramp and trip points to create the variable delay. A slower ramp

time produces more time jitter.

Synchronizing the Outputs—Sync Function

The AD9517 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and subsequently releasing these

outputs to continue clocking at the same instant with the preset

conditions applied. This allows for the alignment of the edges of

two or more outputs or for the spacing of edges according to the

coarse phase offset settings for two or more outputs.

Synchronization of the outputs is executed in several ways,

as follows:

•

By forcing the SYNC pin low and then releasing it (manual

sync).

•

By setting and then resetting any one of the following three

bits: the soft sync bit (Register 0x230[0]), the soft reset bit

(Register 0x000[2] [mirrored]), and the power-down

distribution reference bit (Register 0x230[1]).

•

By executing synchronization of the outputs as part of the

chip power-up sequence.

•

By forcing the RESET pin low and then releasing it (chip

reset).

•

By forcing the PD pin low and then releasing it (chip power-

down).

•

Following completion of a VCO calibration. An internal

SYNC signal is automatically asserted at the beginning of

a VCO calibration and then released upon its completion.

The most common way to execute the sync function is to use

the SYNC pin to do a manual synchronization of the outputs.

This requires a low-going signal on the SYNC pin, which is held

low and then released when synchronization is desired. The

timing of the sync operation is shown in Figure 57 (using VCO

divider) and Figure 58 (VCO divider not used). There is an

uncertainty of up to one cycle of the clock at the input to the

channel divider due to the asynchronous nature of the SYNC

signal with respect to the clock edges inside the AD9517. The

delay from the SYNC rising edge to the beginning of synchronized

output clocking is between 14 and 15 cycles of clock at the

channel divider input, plus either one cycle of the VCO divider

input (see Figure 57), or one cycle of the channel divider input

(see Figure 58), depending on whether the VCO divider is used.

Cycles are counted from the rising edge of the signal.

Another common way to execute the sync function is by setting

and resetting the soft sync bit at Register 0x230[0] (see Table 53

through Table 62 for details). Both the setting and resetting

of the soft sync bit require an update all registers operation

(Register 0x232[0] = 1) to take effect.

AD9517-0A/PCBZ Datenblatt(PDF) 47 Page - Analog Devices

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