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AD9517-0A/PCBZ Datenblatt(PDF) 63 Page - Analog Devices

Teilenummer AD9517-0A/PCBZ
Bauteilbeschribung  12-Output Clock Generator with Integrated 2.8 GHz VCO
PDF  80 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9517-0A/PCBZ Datenblatt(HTML) 63 Page - Analog Devices

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Data Sheet
AD9517-0
Rev. E | Page 63 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01A
6
Reference
frequency monitor
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see
Table 16: REF1, REF2, and VCO frequency status monitor parameter).
threshold
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
[5:0]
LD pin control
Selects the signal that is connected to the LD pin.
5
4
3
2
1
0
Level or
Dynamic
Signal
Signal at LD Pin
0
0
0
0
0
0
LVL
Digital lock detect (high = lock, low = unlock) (default).
0
0
0
0
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
1
HIZ
High-Z LD pin.
0
0
0
1
0
0
CUR
Current source lock detect (110 µA when DLD is true).
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXXb not specified above.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when indifferential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
Not available. Do not use.
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential
mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active
low.
1
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active low.
1
1
0
1
1
1
LVL
Status of REF1 frequency (active low).
1
1
1
0
0
0
LVL
Status of REF2 frequency (active low).
1
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
0
1
1
LVL
Status of VCO frequency (active low).
1
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
1
0
LVL
Holdover active (active low).
1
1
1
1
1
1
LVL
Not available. Do not use.



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