AM79C975VCW datasheet(268/304 Pages) AMD

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APPENDIX C

Am79C973/Am79C975

268

Media Independent Interface (MII)

APPENDIX C: MEDIA INDEPENDENT INTERFACE (MII)

Introduction

The Am79C973/Am79C975 controller fully supports

the MII according to the IEEE 802.3 standard. This

Reconciliation Sublayer interface allows a variety of

PHYs (100BASE-TX, 100BASE-FX, 100BASE-T4,

100BASE-T2, 10BASE-T, etc.) to be attached to the

Am79C973/Am79C975 MAC engine without future up-

grade problems. The MII interface is a 4-bit (nibble)

wide data path interface that runs at 25 MHz for 100-

Mbps networks or 2.5 MHz for 10-Mbps networks. The

interface consists of two independent data paths, re-

ceive (RXD(3:0)) and transmit (TXD(3:0)), control sig-

nals for each data path (RX_ER, RX_DV, TX_ER,

TX_EN), network status signals (COL, CRS), clocks

(RX_CLK, TX_CLK) for each data path, and a two-wire

management interface (MDC and MDIO). See Figure

C-77.

Note: The MII interface is disabled by default. It is en-

abled by setting PHYSELEN (BCR2 bit 13) = 1 and

PHYSEL (BCR18 bit 4, 3) =10.

Enabling the MII interface automatically disables the in-

ternal 10/100 PHY and the Expansion Bus. When in

this mode, the Am79C973/Am79C975 MII interface

pins are multiplexed with the expansion bus pins. Refer

to the connection diagram showing how the pins are

multiplexed.

MII Transmit Interface

The MII transmit clock is generated by the external

PHY and is sent to the Am79C973/Am79C975 control-

ler on the TX_CLK input pin. The clock can run at 25

MHz or 2.5 MHz, depending on the speed of the net-

work to which the external PHY is attached. The data

is a nibble-wide (4 bits) data path, TXD(3:0), from the

Am79C973/Am79C975 controller to the external PHY

and is synchronous to the rising edge of TX_CLK. The

transmit process star ts when the Am79C973/

Am79C975 controller asserts the TX_EN, which indi-

cates to the external PHY that the data on TXD(3:0) is

valid.

Normally, unrecoverable errors are signaled through

the MII to the external PHY with the TX_ER output pin.

The external PHY will respond to this error by generat-

ing a TX coding error on the current transmitted frame.

The Am79C973/Am79C975 controller does not use

this method of signaling errors on the transmit side.

The Am79C973/Am79C975 controller will invert the

FCS on the last byte generating an invalid FCS. The

TX_ER pin is reserved for future use and is actively

driven to 0.

Figure 77. Media Independent Interface

RXD(3:0)

RX_DV

RX_ER

RX_CLK

TXD(3:0)

TX_EN

Am79C973/Am79C975

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

21510C-77

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