AM79C975VCW datasheet(270/304 Pages) AMD

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Am79C973/Am79C975

P R E L I M INARY

Figure 78. Frame Format at the MII Interface Connection

This is followed by a start field (ST) and an operation

field (OP). The operation field (OP) indicates whether

the Am79C973/Am79C975 controller is initiating a read

or write operation. This is followed by the external PHY

address (PHYADD) and the register address (REGAD)

programmed in BCR33. The PHY address of 1Fh is re-

served and should not be used. The external PHY may

have a larger address space starting at 10h - 1Fh. This

is the address range set aside by the IEEE as vendor

usable address space and will vary from vendor to ven-

dor. This field is followed by a bus turnaround field. Dur-

ing a read operation, the bus turnaround field is used to

determine if the external PHY is responding correctly to

the read request or not. The Am79C973/Am79C975

controller will tri-state the MDIO for both MDC cycles.

During the second cycle, if the external PHY is syn-

chronized to the Am79C973/Am79C975 controller, the

external PHY will drive a 0. If the external PHY does not

drive a 0, the Am79C973/Am79C975 controller will sig-

nal a MREINT (CSR7, bit 9) interrupt, if MREINTE

(CSR7, bit 8) is set to a 1, indicating the Am79C973/

Am79C975 controller had an MII management frame

read error and that the data in BCR34 is not valid. The

data field to/from the external PHY is read or written

into the BCR34 register. The last field is an IDLE field

that is necessary to give ample time for drivers to turn

off before the next access. The Am79C973/Am79C975

controller will drive the MDC to 0 and tri-state the MDIO

anytime the MII Management Port is not active.

To help to speed up the reading and of writing the MII

management frames to the external PHY, the MDC can

be sped up to 10 MHz by setting the FMDC bits in

BCR32. The IEEE 802.3 specification requires use of

the 2.5-MHz clock rate, but 5 MHz and 10 MHz are

available for the user. The intended applications are

that the 10-MHz clock rate can be used for a single ex-

ternal PHY on an adapter card or motherboard. The 5-

MHz clock rate can be used for an exposed MII with

one external PHY attached. The 2.5-MHz clock rate is

intended to be used when multiple external PHYs are

connected to the MII Management Port or if compli-

ance to the IEEE 802.3u standard is required.

Auto-Poll External PHY Status Polling

As defined in the IEEE 802.3 standard, the external

PHY attached to the Am79C973/Am79C975 control-

ler’s MII has no way of communicating important timely

status information back to Am79C973/Am79C975 con-

troller. The Am79C973/Am79C975 controller has no

way of knowing that an external PHY has undergone a

change in status without polling the MII status register.

To prevent problems from occurring with inadequate

host or software polling, the Am79C973/Am79C975

controller will Auto-Poll when APEP (BCR32, bit 11) is

set to 1 to insure that the most current information is

available. See MII Management Registers section for

the bit descriptions of the MII Status Register. The con-

tents of the latest read from the external PHY will be

stored in a shadow register in the Auto-Poll block. The

first read of the MII Status Register will just be stored,

but subsequent reads will be compared to the contents

already stored in the shadow register. If there has been

a change in the contents of the MII Status Register, a

MAPINT (CSR7, bit 5) interrupt will be generated on

INTA if the MAPINTE (CSR7, bit 4) is set to 1. The

Auto-Poll features can be disabled if software driver

polling is required.

The Auto-Poll’s frequency of generating MII manage-

ment frames can be adjusted by setting of the APDW

bits (BCR32, bits 10-8). The delay can be adjusted

from 0 MDC periods to 2048 MDC periods. Auto-Poll by

default will only read the MII Status register in the ex-

ternal PHY.

Network Port Manager

The Am79C973/Am79C975 controller is unique in that

is does not require software intervention to control and

configure an external PHY attached to the MII. This

was done to ensure backwards compatibility with exist-

ing software drivers. To the current software drivers, the

Am79C973/Am79C975 controller will look and act like

the PCnet-PCI II and will interoperate with existing

PCnet drivers from revision 2.5 upward. The heart of

this system is the Network Port Manager.

If the external PHY is present and is active, the Net-

work Port Manager will request status from the external

Preamble

1111....1111

10 Rd

01 Wr

PHY

Address

Z0 Rd

10 Wr

Data

Bits

Bit

Idle

21510C-78

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