AM79C975VCW datasheet(272/304 Pages) AMD

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272

Am79C973/Am79C975

P R E L I M INARY

ager will periodically query the external PHY for active

links.

Automatic Network Selection: External PHY

Auto-Negotiable

This case occurs when the MIIPD (BCR32, bit 14) bit is

1. This indicates that there is an external PHY attached

to Am79C973/Am79C975 controller’s MII. If more than

one external PHY is attached to the MII Management

Interface, then the DANAS (BCR32, bit 7) bit must be

set to 1 and then all configuration control should revert

to software. The Am79C973/Am79C975 controller will

read the MII Status register of the external PHY to de-

termine its status and network capabilities. If the exter-

nal PHY is Auto-Negotiation capable and/or the

XPHYANE (BCR32, bit 5) bit is set to 1, then the

Am79C973/Am79C975 controller will start the external

PHY’s Auto-Negotiation process. The Am79C973/

Am79C975 controller will write to the external PHY’s

Advertisement register with the following conditions

set: turn off the Next Pages support, set the Technology

Ability Field from the external PHY MII Status register

read, and set the Type Selector field to the IEEE 802.3

standard. The Am79C973/Am79C975 controller will

then write to the external PHY’s MII Control register in-

structing the external PHY to negotiate the link. The

Am79C973/Am79C975 controller will poll the external

PHY’s MII Status register until the Auto-Negotiation

Complete bit is set to 1and the Link Status bit is set to

1. The Am79C973/Am79C975 controller will then wait

a specific time and then again read the external PHY’s

MII Status register. If the Am79C973/Am79C975 con-

troller sees that the external PHY’s link is down, it will

try to bring up the external PHY’s link manually as de-

scribed above. A new read of the external PHY’s MII

Status register will be made to see if the link is up. If the

link does not come up as programmed after a specific

time, the Am79C973/Am79C975 controller will fail the

external PHY link and start the process again.

Automatic Network Selection: Force External Reset

If the XPHYRST bit (BCR32, bit 6) is set to 1, then the

flow changes slightly. The Am79C973/Am79C975 con-

troller will write to the external PHY’s MII Control regis-

ter wi th the RE SE T bi t s e t to 1 (S e e th e MI I

Management Registers section for the MII register bit

descriptions). This will force a complete reset of the ex-

ternal PHY. The Am79C973/Am79C975 controller after

a specific time will poll the external PHY’s MII Control

bit is cleared, then the normal flow continues.

External Address Detection Interface

The EADI is provided to allow external address filtering

and to provide a Receive Frame Tag word for propri-

etary routing information. It is selected by setting the

EADISEL bit in BCR2 to 1. This feature is typically uti-

lized by terminal servers, bridges and/or router prod-

ucts. The EADI interface can be used in conjunction

with external logic to capture the packet destination ad-

dress from the nibble as it arrives at the Am79C973/

Am79C975 controller, to compare the captured ad-

dress with a table of stored addresses or identifiers,

and then to determine whether or not the Am79C973/

Am79C975 controller should accept the packet.

If an address match is detected by comparison with ei-

ther the Physical Address or Logical Address Filter reg-

isters contained within the Am79C973/Am79C975

controller or the frame is of the type 'Broadcast', then

the frame will be accepted regardless of the condition

of EAR. When the EADISEL bit of BCR2 is set to 1 and

the Am79C973/Am79C975 controller is programmed

to promiscuous mode (PROM bit of the Mode Register

is set to 1), then all incoming frames will be accepted,

regardless of any activity on the EAR pin.

Internal address match is disabled when PROM

(CSR15, bit 15) is cleared to 0, DRCVBC (CSR15, bit

14) and DRCVPA (CSR15, bit 13) are set to 1, and the

Logical Address Filter registers (CSR8 to CSR11) are

programmed to all zeros.

When the EADISEL bit of BCR2 is set to 1 and internal

address match is disabled, then all incoming frames

will be accepted by the Am79C973/Am79C975 control-

ler, unless the EAR pin becomes active during the first

64 bytes of the frame (excluding preamble and SFD).

This allows external address lookup logic approxi-

mately 58 byte times after the last destination address

bit is available to generate the EAR signal, assuming

that the Am79C973/Am79C975 controller is not config-

ured to accept runt packets. The EADI logic only sam-

ples EAR from 2 bit times after SFD until 512 bit times

(64 bytes) after SFD. The frame will be accepted if EAR

has not been asserted during this window. In order for

the EAR pin to be functional in full-duplex mode, FDR-

PAD bit (BCR9, bit 2) needs to be set. If Runt Packet

Accept (CSR124, bit 3) is enabled, then the EAR signal

must be generated prior to the 8 bytes received, if

frame rejection is to be guaranteed. Runt packet sizes

could be as short as 12 byte times (assuming 6 bytes

for source address, 2 bytes for length, no data, 4 bytes

for FCS) after the last bit of the destination address is

available. EAR must have a pulse width of at least 110

ns.

The EADI outputs continue to provide data throughout

the reception of a frame. This allows the external logic

to capture frame header information to determine pro-

tocol type, internetworking information, and other use-

ful data.

The EADI interface will operate as long as the STRT bit

in CSR0 is set, even if the receiver and/or transmitter

are disabled by software (DTX and DRX bits in CSR15

are set). This configuration is useful as a semi-power-

down mode in that the Am79C973/Am79C975 control-

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