AMMCL002AWP datasheet(11/36 Pages) AMD

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AmMCL00XA

PRELIMIN ARY

Table 4.

Miniature Card Read/Write Modes

Notes:

1. Unlisted access combinations are invalid and may return unexpected results.

2. X indicates a don’t care value.

Erase Operations

The AMD Flash Miniature Card is organized as an

array of individual devices. Each Am29LV081 device

contains sixteen 64 KByte sectors, for a total of 1 Mbyte

of memory space per device.

Flash technology allows any logical “1” data bit to be pro-

grammed to a logical “0”. The only way to reset bits to a

logical “1” is to erase that entire memory sector or

memory device. Once a memory sector or memory

device is erased, any address location may be pro-

grammed. Two or more devices may be erased concur-

rently when additional ICC current is supplied to the card.

However, erasing more than two devices concurrently is

not typical in battery-powered applications, but may take

place during procedures such as card testing.

Erase operations can be performed in several ways:

s Erase a single sector or multiple sectors in a device

s Erase a sector pair

s Erase multiple device pairs*

s Erase the entire card*

* This operation is only feasible in solutions capable of

supplying more than the specified miniature card

supply current requirement (150mA) per system. Each

AMD Flash memory device pair can accept a

maximum of 120mA supply current.

The common memory space data contents are altered

in a similar manner to writing to individual Flash

memory devices. An on-card address decoder acti-

vates the appropriate Flash device in the memory

array. Each device internally latches address and data

during write cycles. Refer to Table 4.

Standby Mode

The AMD flash devices are designed to accommodate

low standby power consumption. In order to achieve

standby mode, the CE# line must be deselected. In

addition, while in the standby mode, data I/O pins

remain in the high impedance state independent of the

voltage level applied to the OE# input. See the DC

Characteristics section for more details on Standby

Modes.

Deselecting CE# (CE# and RESET# = VCC ± 0.3 V)

puts the device into the ICC3 standby mode. If the

device is deselected during an Embedded Algorithm

operation, it continues to draw active power (ICC2) prior

to entering the standby mode, until the operation is

complete. When the device is again selected (CE# =

VIL), active operations occur in accordance with the

AC timing specifications.

Automatic Sleep Mode

Advanced power management features such as the

automatic sleep mode minimize Flash device energy

consumption. This is extremely important in bat-

tery-powered applications. The AMD memory devices

automatically enable the low-power, automatic sleep

mode when addresses remain stable for 300 ns. Auto-

matic sleep mode is independent of the CE#, WE#, and

OE# control signals. Typical sleep mode current draw

from each device is < 1

µA. Standard address access

timings provide new data when addresses are

Function

CEH#

CEL#

WE#

OE#

D8–D15

D0–D7

Read Mode

Word Access

High Byte Data

Low Byte Data

Low Byte Access

High-Z

Low Byte Data

High Byte Access

High Byte Data

High-Z

Write Mode

Word Access

High Byte Data

Low Byte Data

Low Byte Access

High-Z

Low Byte Data

High Byte Access

High Byte Data

High-Z

Standby Mode

Standby

High-Z

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