AMMCL002AWP datasheet(17/36 Pages) AMD

17 / 36 page

AmMCL00XA

PRELIMIN ARY

Hardware Reset is initiated. Loading the sector erase

registers may be done in any sequence and with any

number of sectors (0 to 15).

A Reset command issued after the device has begun

execution stops the erase operation, but the data in the

sector will be undefined. In that case, restart the erase

on that sector and allow it to complete.

The automatic sector erase begins after the 80

µs time

out from the rising edge of the WE# (or CE#) pulse for

the last sector erase command pulse and terminates

when the data on D7 is “1” (see Write Operation Status

section) at which time the device returns to read mode.

Data Polling must be performed at an address within

any of the sectors being erased.

If DATA Polling or the Toggle Bit indicates the device

has been written with a valid Sector Erase command,

D3 may be used to determine if the sector erase timer

window is still open. If D3 is high (‘1’), the internally

controlled erase cycle has begun; attempts to write

subsequent commands to the device will be ignored

until the erase operation is completed as indicated by

the DATA Polling or Toggle Bit. If D3 is low (‘0’), the

device will accept additional sector erase commands.

To be certain the command has been accepted, the

software should check the status of D3 following each

Sector Erase command. If D3 was high on the second

status check, the command may not have been

accepted.

It is recommended that the user guarantee the time

between sector erase command writes be less than 80

µs by disabling the processor interrupts just for the

duration of the Sector Erase (30H) commands. This

approach will ensure that sequential sector erase

command writes will be written to the device while the

sector erase timer window is still open.

Figure 4 illustrates the Embedded Erase Algorithm

using typical command strings and bus operations.

Table 9.

Embedded Erase Algorithm

Figure 4.

Embedded Erase Algorithm

Note: The latest release of the software drivers for AMD

Miniature Cards and devices may be downloaded from the

AMD web site at http://www.amd.com.

Embedded Program Algorithm

The Embedded Program setup is a four bus cycle oper-

ation that stages the addressed memory location or

memory device for automatic programming.

Once the Embedded Program setup operation is per-

formed, the next WE# pulse causes a transition to an

active programming operation. Addresses are inter-

nally latched on the falling edge of the WE# (or CE#)

pulse. Data is internally latched on the rising edge of

the WE# pulse. The rising edge of WE# also begins the

programming operation. The system is not required to

provide further control or timing. The device will auto-

matically provide an adequate internally generated

write pulse and verify margin. The automatic program-

ming operation is completed when the data on D7 of

the addressed memory sector or memory device is

equivalent to data written to this bit (see Write Opera-

tion Status section) at which time the device returns to

the Read mode (no write verify command is required).

Addresses are latched on the falling edge of WE# (or

CE#

) during the Embedded Program command execu-

tion and hence the system is not required to keep the

addresses stable during the entire Programming opera-

tion. However, once the device comple te s the

Embedded Program operation, it returns to the Read

mode and addresses are no longer latched. Since a

verify valid data must occur on D7, at this particular

instant, the system is required to supply a valid address

input to the device. A system designer has three choices

to implement the Embedded Programming algorithm:

Bus

Operation

Command

Comments

Standby

Wait for VCC ramp

Write

Embedded Erase

command sequence

6 bus cycle operation

Read

Data Poll or check

BUSY# (RY/BY#)

to verify erasure

Write Embedded Erase

Command Sequence

(See Tables 5–7)

Data Poll from Device

or wait for BUSY#

(RY/BY#)

Start

Erasure Complete

21138E-5

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