AMMCL002AWP datasheet(16/36 Pages) AMD

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AmMCL00XA

PR EL IMIN A R Y

AMD FLASH MEMORY PROGRAM AND

ERASE OPERATIONS

To simplify program and erase operations, AMD Flash

Memory devices include Embedded Algorithms

(Embedded Erase Algorithm and Embedded Program

Algorithm) that allow the host to simply issue a com-

mand, after which it is free to perform other tasks. The

host then only needs to monitor appropriate status bits

to determine when the operation is complete.

Embedded Erase Algorithm

When erasing a sector or device, the Embedded Erase

algorithm does not require the host to first entirely

p r e - pr ogr a m t h e de vice. U pon exe c uting th e

Embedded Erase command sequence, the addressed

memory sector or memory device automatically writes

and verifies the entire memory device or memory

sector for an all “0” data pattern. The system is not

required to provide any controls or timing during these

operations.

When the memory sector or memory device is auto-

matically verified to contain an all “0” pattern, a

self-timed chip erase-and-verify begins. The erase and

verify operations are complete when the data on D7

(D15 on the odd byte) of the memory sector or memory

device is “1” (see Write Operation Status section), at

which time the device returns to the read mode. The

system is not required to provide any control or timing

during these operations. If a Reset command is issued

while the erase operation is in progress, the erase

operation will stop, and the data in that device will be

undefined. In that case, restart the erase on that sector

a n d a llo w i t t o c omp lete .

When using the Embedded Erase algorithm, the erase

automatically terminates when adequate erase margin

has been achieved for the memory array (no erase

verify command is required).

The Embedded Erase command sequence is a

command only operation that stages the memory

sector or memory device for automatic electrical

erasure of all bytes in the array. The automatic erase

begins on the rising edge of the WE# and terminates

when the data on D7 (D15 on the odd byte) of the

memory sector or memory device is “1” (see Write

Operation Status section) at which time the device

returns to the Read mode. Please note that for the

memory device or memory sector erase operation,

Data Polling may be performed at any address in that

device or sector.

Figure 4 and Table 9 illustrate the Embedded Erase

Algorithm, a typical command string and bus operations.

As described earlier, once the memory sector in a

device or memory device completes the Embedded

Erase operation, it returns to the Read mode and

addresses are no longer latched. Therefore, the device

requires that a valid address input to the device is

supplied by the system at this particular instant of time.

Otherwise, the system will never read a “1” on D7 (D15

on the odd byte). A system designer has the following

choices to implement the Embedded Erase algorithm:

1. The host may keep the sector address (within any

of the sectors being erased) valid during the entire

Embedded Erase operation.

2. Once the system executes the Embedded Erase

command sequence, the host may remove the ad-

dress from the device and perform other tasks. The

host is required to keep track of the valid sector ad-

dress by loading it into a temporary register. When

the host comes back to Data Poll the device, it must

reassert the same address.

3. The host may monitor BUSY# (RY/BY#) to deter-

mine the status of the Embedded Algorithm in

progress. A “0” indicates that the device is busy; a

“1” indicates that the algorithm is complete.

Sector Erase

Sector erase is a six bus cycle operation. There are two

“unlock” write cycles. These are followed by writing the

“set-up” command. Two more “unlock” write cycles are

then followed by the sector erase command. The

sector address (any address location within the desired

sector) is latched on the falling edge of WE# (or CE#),

whichever occurs later, while the data is latched on the

rising edge of WE# (or CE#) pulse, whichever occurs

first. A time-out of 80

µs from the rising edge of the last

sector erase command will initiate the sector erase

com mand .

Multiple sectors can be specified for erase by writing

the six bus cycle operation as described above and

then following it by additional writes of the Sector Erase

command to addresses of other sectors to be erased.

The time between Sector Erase command writes must

be less than 80

µs, otherwise that command will not be

accepted. It is recommended that processor interrupts

be disabled during this time to guarantee this condition.

The interrupts can be re-enabled after the last Sector

Erase command is written. A time-out of 80

µs from the

rising edge of the last WE# (or CE#) will initiate the ex-

ecution of the Sector Erase command(s). If another

falling edge of the WE# (or CE#) occurs within the 80

µs time-out window, the timer is reset. During the 80 µs

window, any command other than Sector Erase or

Erase Suspend written to the device will reset the de-

vice back to Read mode. Once the 80

µs window has

timed out, only the Erase suspend command is recog-

nized. Note that although the Reset command is not

recognized in the Erase Suspend mode, the device is

available for read or program operations in sectors that

are not erase suspended. The Erase Suspended and

Erase Resume commands may be written as often as

required during a sector erase operation. Hence, once

erase has begun, it must ultimately complete unless

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