AD9524SLASHPCBZ datasheet(48/56 Pages) AD

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AD9524

Data Sheet

Rev. E | Page 48 of 56

Table 48. VCO Control

Address

Bits

Bit Name

Description

0x0F3

[7:5]

Reserved

Reserved.

Force release of distribution sync

when PLL2 is unlocked

0 (default): distribution is held in sync (static) until the output PLL locks. Then it is

automatically released from sync with all dividers synchronized.

1: overrides the PLL2 lock detector state; forces release of the distribution from

sync.

Reserved

0 (default): value must remain 0.

Force VCO to midpoint frequency

Selects VCO control voltage functionality.

0 (default): normal VCO operation.

1: forces VCO control voltage to midscale.

Calibrate VCO (not autoclearing)

1: initiates VCO calibration (this is not an autoclearing bit).

0: resets the VCO calibration.

Reserved

Reserved.

Table 49. VCO Divider Control

Address

Bits

Bit Name

Description

0x0F4

[7:4]

Reserved

Reserved.

VCO divider power-down

1: powers down the divider.

0: normal operation.

[2:0]

VCO divider

Note that the VCO divider connects to all output channels.

Bit 2

Bit 1

Bit 0

Divider Value

Divide-by-4

Divide-by-5

Divide-by-6

Divide-by-7

Divide-by-8

Divide-by-9

Divide-by-10

Divide-by-11

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