AD9524SLASHPCBZ datasheet(13/56 Pages) AD

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Data Sheet

AD9524

Rev. E | Page 13 of 56

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW

(Not to Scale)

AD9524

REFA

REFB

LF1_EXT_CAP

OSC_CTRL

OSC_IN

LF2_EXT_CAP

LDO_PLL2

VDD3_PLL2

LDO_VCO

VDD1.8_OUT[2:3]

OUT2

VDD3_OUT[2:3]

OUT3

EEPROM_SEL

RESET

REF_TEST

STATUS0/SP0

STATUS1/SP1

NOTES

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.

AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.

ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 42 CONNECTED TO 1.8V SUPPLY.

2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE

SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY

AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 2. Pin Configuration

Table 19. Pin Function Descriptions

No.

Mnemonic

Type1

Description

REFA

Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REFA

Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for

the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.

REFB

Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REFB

Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for

the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

LF1_EXT_CAP

PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground.

OSC_CTRL

Oscillator Control Voltage. Connect this pinto the voltage control pin of the external oscillator.

OSC_IN

PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

OSC_IN

Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

LF2_EXT_CAP

PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO.

LDO_PLL2

P/O

LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 μF decoupling capacitor

from this pin to ground. Note that for best performance, the LDO bypass capacitor must be

placed in close proximity to the device.

VDD3_PLL2

3.3 V Supply for PLL2.

LDO_VCO

P/O

2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor

from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be

placed in close proximity to the device.

SYNC

Manual Synchronization. This pin initiates a manual synchronization and has an internal

40 kΩ pull-up resistor.

VDD3_REF

3.3 V Supply for Output Clock Drivers Reference.

Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.

SCLK/SCL

Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming.

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