Data Sheet

AD9524

Rev. E | Page 5 of 56

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON

Channel x control register, Bit 4 = 1

LVDS Mode, 7 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

10

10.8

mA

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

27

29.8

mA

f = 983.04 MHz

LVDS Mode, 3.5 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

6.5

7.5

mA

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

23

26.3

mA

f = 983.04 MHz

LVPECL Compatible Mode

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

11

12.4

mA

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

28

31.2

mA

f = 983.04 MHz

HSTL Mode, 16 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

20

24.3

mA

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

50

59.1

mA

f = 983.04 MHz

HSTL Mode, 8 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

11

12.7

mA

f = 122.88 MHz

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

27

31.8

mA

f = 983.04 MHz

1

x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,

respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).

2

The current for Pin 34 (VDD1.8_OUT[0:3]) is 2× that of the other VDD1.8_OUT[x:y] pairs.