AD9524SLASHPCBZ datasheet(24/56 Pages) AD

24 / 56 page

AD9524

Data Sheet

Rev. E | Page 24 of 56

Clock Distribution Synchronization

A block diagram of the clock distribution synchronization

functionality is shown in Figure 27. The synchronization

sequence begins with the primary synchronization signal,

which ultimately results in delivery of a synchronization strobe

to the clock distribution logic.

As indicated, the primary synchronization signal originates

from one of the following sources:



Direct synchronization source via the sync dividers bit (see



Device pin, SYNC (Pin 13)

An automatic synchronization of the divider is initiated the first

time that PLL2 locks after a power-up or reset event. Subsequent

lock/unlock events do not initiate a resynchronization of the

distribution dividers unless they are preceded by a power-down

or reset of the part.

FAN OUT

VCO OUTPUT DIVIDER

SYNC (PIN 13)

SYNC

DIVIDER

DRIVER

OUTx

OUT

SYNC

PHASE

DIVIDE

SYNC DIVIDERS BIT

Figure 27. Clock Output Synchronization Block Diagram

DIVIDE = 2, PHASE = 0

DIVIDE = 2, PHASE = 6

VCO DIVIDER OUTPUT CLOCK

SYNC

CONTROL

6 × 0.5 PERIODS

Figure 28. Clock Output Synchronization Timing Diagram

AD9524/PCBZ Datenblatt(PDF) 24 Page - Analog Devices