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PRIXP425BD Datenblatt(PDF) 92 Page - Intel Corporation |
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PRIXP425BD Datenblatt(HTML) 92 Page - Intel Corporation |
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92 / 112 page ![]() Intel® IXP42X Product Line and IXC1100 Control Plane Processor Electrical Specifications 92 Datasheet NOTE: 1. This parameter is not tested and is guaranteed by design. 5.5.2.6 SDRAM Bus Table 49. MDIO Timings Values Symbol Parameter Min. Max. Units Notes T1 ETH_MDIO, clock to output timing with respect to rising edge of ETH_MDC clock ETH_MDC/2 + 10 ns ns T2 ETH_MDIO output hold timing after the rising edge of ETH_MDC clock 10 ns T3 ETH_MDIO input setup prior to rising edge of ETH_MDC clock 2 ns T4 ETH_MDIO hold time after the rising edge of ETH_MDC clock 0 ns T5 ETH_MDC clock period 125 500 ns 1 Figure 23. SDRAM Input Timings Table 50. SDRAM Input Timings Values Symbol Parameter Min. Max. Units Notes Tsetup Input setup prior to rising edge of clock. Inputs included in this timing are SDM_DQ[31:0] (during a read operation). 1.4 ns Thold Input hold time after the rising edge of the clock. Inputs included in this timing are SDM_DQ[31:0] (during a read operation). 1.5 ns Tsetup Thold Clock Signals |
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