PRIXP425BD datasheet(27/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Overview

Datasheet

The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways and each way

contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word),

and a line-valid bit. For each of the 32 sets, 0 through 28 ways can be locked. Unlocked ways are

replaceable via a round-robin policy.

The I-cache can be enabled or disabled. Attribute bits within the descriptors — contained in the

ITLB of the IMMU — provide some control over an enabled I-cache.

When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical

word first) from memory via a two-level, deep-fetch queue. The fetch queue allows the next

instruction to be accessed from the I-cache, but only when its data operands do not depend on the

execution results of the instruction being fetched via the queue.

2.2.6

Data Cache (D-Cache)

The D-cache can contain high-use data such as lookup tables and filter coefficients, allowing the

core access to data at core frequencies. This prevents core stalls caused by multi-cycle accesses to

external memory.

The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways and each

way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty

bits (one for each of two eight-byte groupings in a line), and one valid bit. For each of the 32 sets,

zero through 28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are

replaceable via a round-robin policy.

The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within

the descriptors, contained in the DTLB of the DMMU, provide significant control over an enabled

D-cache. These bits specify cache operating modes such as read and write allocate, write-back,

write-through, and D-cache versus mini-data cache targeting.

The D-cache (and mini-data cache) work with the load buffer and pend buffer to provide

“hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is

encountered. The D-cache (and mini-data cache) works in conjunction with the write buffer for

data that is to be stored to memory.

2.2.7

Mini-Data Cache

The mini-data cache can contain frequently changing data streams such as MPEG video, allowing

the core access to data streams at core frequencies. This prevents core stalls caused by multi-cycle

accesses to external memory. The mini-data cache relieves the D-cache of data “thrashing” caused

by frequently changing data streams.

The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains two ways and

each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two

dirty bits (one for each of two eight-byte groupings in a line), and a valid bit. The mini-data cache

uses a round-robin replacement policy, and cannot be locked.

The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute bits

contained within a coprocessor register specify operating modes write and/or read allocate,

write-back, and write-through.

PRIXP425BD Datenblatt(PDF) 27 Page - Intel Corporation

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