PRIXP425BD datasheet(33/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

Table 6.

PCI Controller (Sheet 1 of 2)

Name

Power

Reset†

Reset† Type†

Description

PCI_AD[31:0]

I/O

PCI Address/Data bus used to transfer address and bidirectional data to

and from multiple PCI devices.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

PCI_CBE_N[3:0]

I/O

PCI Command/Byte Enables is used as a command word during PCI address

cycles and as byte enables for data cycles.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_PAR

I/O

PCI Parity used to check parity across the 32 bits of PCI_AD and the

four bits of PCI_CBE_N.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

PCI_FRAME_N

I/O

PCI Cycle Frame used to signify the beginning and duration of a

transaction. The signal will be inactive prior to or during the final data

phase of a given transaction.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_TRDY_N

I/O

PCI Target Ready informs that the target of the PCI bus is ready to

complete the current data phase of a given transaction.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_IRDY_N

I/O

PCI Initiator Ready informs the PCI bus that the initiator is ready to

complete the transaction.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_STOP_N

I/O

PCI Stop indicates that the current target is requesting the current initiator

to stop the current transaction.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_PERR_N

I/O

PCI Parity Error asserted when a PCI parity error is detected — between the

PCI_PAR and associated information on the PCI_AD bus and PCI_CBE_N —

during all PCI transactions, except for Special Cycles. The agent receiving

data will drive this signal.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_SERR_N

I/OD

PCI System Error asserted when a parity error occurs on special cycles or

any other error that will cause the PCI bus not to function properly. This

signal can function as an input or an open drain output.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_DEVSEL_N

I/O

PCI Device Select:

• When used as an output, PCI_DEVSEL_N indicates that device has

decoded that address as the target of the requested transaction.

• When used as an input, PCI_DEVSEL_N indicates if any device on

the PCI bus exists with the given address.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_IDSEL

PCI Initialization Device Select is a chip select during configuration reads

and writes.

Should be pulled low with a 10-K

Ω resistor when not being utilized in the

system.

PCI_REQ_N[3:1]

PCI arbitration request: Used by the internal PCI arbiter to allow an agent

to request the PCI bus.

Should be pulled high with a 10-K

Ω resistor when not being utilized in the

system.

PCI_REQ_N[0]

I/O

PCI arbitration request:

• When configured as an input (PCI arbiter enabled), the internal PCI

arbiter will allow an agent to request the PCI bus.

• When configured as an output (PCI arbiter disabled), the pin will be

used to request access to the PCI bus from an external arbiter.

Should be pulled high with a 10-K

Ω resistor, when the PCI bus is not being

utilized in the system.

PCI_GNT_N[3:1]

PCI arbitration grant: Generated by the internal PCI arbiter to allow an

agent to claim control of the PCI bus.

†

For a legend of the Type codes, see Table 4 on page 30.

PRIXP425BD Datenblatt(PDF) 33 Page - Intel Corporation

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