PRIXP425BD datasheet(39/112 Pages) INTEL

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Intel® IXP42X Product Line and IXC1100 Control Plane Processor

Functional Signal Descriptions

Datasheet

Power

Table 12.

UART Interfaces

Name

Power

Reset†

Reset† Type†

Description

RXDATA0

UART serial data input to High-Speed UART Pins.

Should be pulled low through a 10-K

Ω resistor when not being utilized in the

system.

TXDATA0

UART serial data output. The TXD signal is set to the MARKING (logic 1) state

upon a reset operation. High-Speed Serial UART Pins.

CTS0_N

VI/PE

UART CLEAR-TO-SEND input to High-Speed UART Pins.

When logic 0, this pin indicates that the modem or data set connected to the

UART interface of the processor is ready to exchange data. The CTS_N signal is

a modem status input whose condition can be tested by the processor.

Should be pulled high through a 10-K

Ω resistor when not being utilized in the

system.

RTS0_N

VO/PE

UART REQUEST-TO-SEND output:

When logic 0, this informs the modem or the data set connected to the UART

interface of the processor that the UART is ready to exchange data. A reset sets

the request to send signal to logic 1.

LOOP-mode operation holds this signal in its inactive state (logic 1). High-Speed

UART Pins.

RXDATA1

UART serial data input.

Should be pulled low through a 10-K

Ω resistor when not being utilized in the

system.

TXDATA1

UART serial data output. The TXD signal is set to the MARKING (logic 1) state

upon a Reset operation. Console UART Pins.

CTS1_N

VI/PE

UART CLEAR-TO-SEND input to Console UART pins.

When logic 0, this pin indicates that the modem or data set connected to the

UART interface of the processor is ready to exchange data. The CTS_N signal is

a modem status input whose condition can be tested by the processor.

Should be pulled high through a 10-K

Ω resistor when not being utilized in the

system.

RTS1_N

VO/PE

UART REQUEST-TO-SEND output:

When logic 0, this informs the modem or the data set connected to the UART

interface of the processor that the UART is ready to exchange data. A reset sets

the request to send signal to logic 1.

LOOP-mode operation holds this signal in its inactive state (logic 1). Console

UART Pins.

†

For a legend of the Type codes, see Table 4 on page 30.

Table 13.

USB Interface

Name

Power

Reset†

Type†

Description

USB_DPOS

I/O

Positive signal of the differential USB receiver/driver.

USB_DNEG

I/O

Negative signal of the differential USB receiver/driver.

†

For a legend of the Type codes, see Table 4 on page 30.

PRIXP425BD Datenblatt(PDF) 39 Page - Intel Corporation

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