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ZIOL2102 Datenblatt(PDF) 2 Page - List of Unclassifed Manufacturers

Teilenummer ZIOL2102
Bauteilbeschribung  IO-Link compliant HV Line Driver IC Family
PDF  91 Pages
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ZIOL2102 Datenblatt(HTML) 2 Page - List of Unclassifed Manufacturers

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ZIOL2xxx – IC Family
IO-Link compliant HV Line Driver IC Family
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
2 of 90
Contents
1
The ZIOL2xxx IC Family Overview .......................................................................................6
2
Electrical Characteristics ......................................................................................................7
2.1. Absolute Maximum Ratings ............................................................................................7
2.2. Operating Conditions ......................................................................................................8
2.3. Electrical Parameters ......................................................................................................9
3
Detailed Description............................................................................................................15
3.1. Block schematic ............................................................................................................15
3.2. Dual Channel Transceiver.............................................................................................16
3.2.1. IC Data Path Configuration......................................................................................16
3.2.2. Transmitter ..............................................................................................................20
3.2.3. Receiver ..................................................................................................................22
3.3. System Control .............................................................................................................24
3.3.1. General....................................................................................................................24
3.3.2. IO-Link Master and Device Mode ............................................................................25
3.3.3. Internal Exceptions ..................................................................................................25
3.3.4. IO-Link specific Wake-Up (WURQ)..........................................................................25
3.3.5. IC Self-Protection – Lock Mode ...............................................................................27
3.3.6. Channel Locking in Master/Device Mode ................................................................29
3.3.7. Memory Unit ............................................................................................................29
3.3.8. Serial Peripheral Interface (SPI) ..............................................................................31
3.3.9. Register Table / Registers for IC Configuration and Monitoring...............................36
3.3.10.Interrupt and IC Lock Mode Control.........................................................................46
3.3.11.Die Temperature Measurement ...............................................................................54
3.4. Smart Power Supply .....................................................................................................54
3.5. The Power Fail Detector ...............................................................................................56
3.5.1. Overview..................................................................................................................56
3.5.2. Line-Fault Detector ..................................................................................................56
3.5.3. Under-voltage Detector............................................................................................57
3.5.4. Channel Locking and Interrupt Generation ..............................................................57
3.5.5. Downward Compatibility ..........................................................................................57



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