IO13PDB0V0 datasheet(30/197 Pages) MICROSEMI

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SmartFusion DC and Switching Characteristics

2- 18

R e v i sio n 1 2

Microcontroller Subsystem Dynamic Contribution—PMSS

SoC Mode

PMSS = PAC22

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some

examples:

•

The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

non-tristate output buffers are used, the enable rate should be 100%.

Table 2-17 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Guideline

α1

Toggle rate of VersaTile outputs

10%

α2

I/O buffer toggle rate

10%

Table 2-18 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

Guideline

β1

I/O output buffer enable rate

Toggle rate of the logic driving the

output buffer

β2

FPGA fabric SRAM enable rate for read

operations

12.5%

β3

FPGA fabric SRAM enable rate for write

operations

12.5%

β4

eNVM enable rate for read operations

< 5%

IO13PDB0V0 Datenblatt(PDF) 30 Page - Microsemi Corporation

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