IO13PDB0V0 datasheet(16/197 Pages) MICROSEMI

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SmartFusion DC and Switching Characteristics

2- 4

R ev isio n 1 2

Power Supply Sequencing Requirement

SmartFusion cSoCs have an on-chip 1.5 V regulator, but usage of an external 1.5 V supply is also

allowed while the on-chip regulator is disabled. In that case, the 3.3 V supplies (VCC33A, etc.) should be

powered before 1.5 V (VCC, etc.) supplies. The 1.5 V supplies should be enabled only after 3.3 V

supplies reach a value higher than 2.7 V.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every SmartFusion cSoC. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-6.

There are five regions to consider during power-up.

SmartFusion I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCxxxxIOBx are above the minimum specified trip points (Figure 2-1 on page 2-6).

2. VCCxxxxIOBx > VCC – 0.75 V (typical)

3. Chip is in the SoC Mode.

Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits

Product Grade

Storage Temperature

Element

Grade Programming

Cycles

Retention

Commercial

Min. TJ = 0°C

FPGA/FlashROM

500

20 years

Max. TJ = 85°C

Embedded Flash

< 1,000

20 years

< 10,000

10 years

< 15,000

5 years

Industrial

Min. TJ = –40°C

FPGA/FlashROM

500

20 years

Max. TJ = 100°C

Embedded Flash

< 1,000

20 years

< 10,000

10 years

< 15,000

5 years

Table 2-5 • Overshoot and Undershoot Limits 1

VCCxxxxIOBx

Average VCCxxxxIOBx–GND Overshoot or Undershoot

Duration as a Percentage of Clock Cycle2

Maximum Overshoot/

Undershoot2

2.7 V or less

10%

1.4 V

1.49 V

3 V

10%

1.1 V

1.19 V

3.3 V

10%

0.79 V

0.88 V

3.6 V

10%

0.45 V

0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

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