LTC1154 datasheet(6/16 Pages) LINER

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LTC1154

PI FU CTIO S

Drain Sense Pin

The drain sense pin is compared against the supply pin

voltage. If the voltage at this pin is more than 100mV below

the supply pin, the input latch will be reset and the MOSFET

gate will be quickly discharged. Cycle the input, or ENABLE

input, to reset the short-circuit latch and turn the MOSFET

back on.

This pin is also a high impedance CMOS gate with ESD

protection and therefore should not be forced beyond the

power supply rails. To defeat the over current protection,

short the drain sense to supply.

Some loads, such as large supply capacitors, lamps, or

motors require high in-rush currents. An RC time delay

can be added between the sense resistor and the drain

sense pin to ensure that the drain sense circuitry does not

false-trigger during start-up. This time constant can be set

from a few microseconds to many seconds. However, very

long delays may put the MOSFET in risk of being destroyed

by a short-circuit condition. (see Applications Information

Section).

Status Pin

The status pin is an open-drain output which is driven low

whenever a fault condition is detected. A 51k pull-up

resistor should be connected between this output and a

logic supply. The status pins of multiple LTC1154s can be

OR’d together if independent fault sensing is not required.

No connection is required to this pin when not in use.

DAGRA

BLOCK

GATE CHARGE

AND DISCHARGE

CONTROL LOGIC

SHUTDOWN

TTL-TO-CMOS

CONVERTER

OSCILLATOR

AND CHARGE

PUMP

FAST/SLOW

GATE CHARGE

LOGIC

FAULT DETECTION

AND STATUS

OUTPUT DRIVER

100mV

REFERENCE

ANALOG SECTION

INPUT

LATCH

GATE

SHUTDOWN

DRAIN

SENSE

ONE

SHOT

TTL-TO-CMOS

CONVERTER

VOLTAGE

REGULATORS

ANALOG

DIGITAL

GND

LOW STANDBY

CURRENT

REGULATOR

INPUT

STATUS

µs

DELAY

LTC1154 • BD01

ENABLE

COMP

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