UPD75P218KB datasheet(20/36 Pages) NEC

20 / 36 page

µPD75P218

Conditions

Main system

clock

Subsystem

clock

VDD = 4.5 to 6.0 V

Parameter

Note 1

CPU clock cycle time

(minimum instruction execu-

tion time = 1 machine cycle)

TI0 input frequency

TI0 input low- and high-level

width

SCK cycle time

SCK low- and high-level width

SI setup time (to SCK

↑)

SI hold time (from SCK

↑)

SCK

↓ → SO output delay

time

Interrupt inputs

low- and high-level width

RESET low-level width

AC Characteristics (Ta = –40 to +70 ˚C, V DD = 2.7 to 6.0 V)

MAX.

125

0.6

165

300

1000

Unit

µs

MHz

kHz

µs

TYP.

122

MIN.

0.67

2.6

114

0.83

0.8

0.95

3.2

3.8

0.4

tKCY/2–50

1.6

tKCY/2–150

100

400

Note 2

2tCY

Symbol

tCY

fTI

tTIH,

tTIL

tKCY

tKH,

tKL

tSIK

tKSI

tKSO

tINTH,

tINTL

tRSL

VDD = 4.5 to 6.0 V

Input

Output

Input

Output

Input

Output

Input

Output

INT0

INT1

INT2,4

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