ADP1055ACPZ-R7 datasheet(19/140 Pages) AD

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Data Sheet

ADP1055

Rev. A | Page 19 of 140

CONTROL LOOP AND PWM OPERATION

VOLTAGE SENSE, FEEDBACK, AND CONTROL LOOP

The VS± pins are used for the monitoring and protection of the

remote load voltage. The differential VS± input pins are the main

feedback sense point for the power supply control loop. The VS±

sense point on the power rail requires an external resistor divider

to bring the nominal common-mode signal to 1 V at the VS± pins.

This resistor divider is programmed into VOUT_SCALE_LOOP

and VOUT_SCALE_MONITOR accordingly. The resistor divider

is necessary because the input range is 0 V to 1.6 V. The

divided-down signal is internally fed into a high frequency (HF)

ADC. The HF ADC is also the high frequency feedback loop for

the power supply.

OUTPUT VOLTAGE SENSE

The output voltage is fed back to the VS± pins, where it is com-

pared with a reference set by a 12-bit DAC (see Figure 22). The

difference is then fed into the flash ADC; in this configuration,

the flash ADC does not see the fraction of the output voltage set

by the resistor divider, but instead sees only the error voltage. The

error voltage is then fed into the digital filter, which decides the

duty cycle command for the next switching period. The number

of samples taken by the flash ADC can be configured in Register

0xFE67[7:4] (see Table 215). The recommended configuration

of this register is automatically configured using the GUI.

Figure 22. Output Voltage Sense and Feedback

The output voltage is also sampled using a low frequency ADC.

The output voltage is fed to a low-pass filter that is used to set the

output of a trim DAC; the trim DAC finely adjusts the output

voltage as part of the autocorrection loop (see the Voltage Loop

Autocorrection section).

DIGITAL FILTER

The loop response of the power supply can be changed using the

internal programmable digital filter. A Type 3 filter architecture

has been implemented. To tailor the loop response to the specific

application, the low frequency gain, zero location, pole location,

and high frequency gain can all be set individually (see the Digital

Filter Programming Registers section). It is recommended that

the Analog Devices, Inc., software GUI be used to program the

filter. The software GUI displays the filter response in Bode plot

format and can be used to calculate all stability criteria for the

power supply.

From the sensed voltage to the duty cycle, the transfer function

of the filter in z-domain is as follows:

























 











 











ADD_PZ

HFG

LFG

H(z)

256

)

(

where:

A = filter pole register value (in decimal).

B = filter zero register value (in decimal).

C = high frequency gain register value (in decimal).

D = low frequency gain register value (in decimal).

LFG = 5.968 × m × 106/fSW.

HFG = 3.73× m × 105/fSW.

m = 1 when 48.8 kHz ≤ fSW < 97.7 kHz.

m = 2 when 97.7 kHz ≤ fSW < 195.3 kHz.

m = 4 when 195.3 kHz ≤ fSW < 390.6 kHz.

m = 8 when 390.6 kHz ≤ fSW.

ADD_PZ is an additional pole or additional zero that can be

added to the compensator.

The additional zero takes this form:

256







The additional pole takes this form:

















1

256

where E is the value (in decimal) of the additional pole zero

frequency gain register (Register 0xFE60 and Register 0xFE61).

To transfer the z-domain value to the s-domain, plug the follow-

ing bilinear transformation equation into the H(z) equation:

z(s)







where fSW is the switching frequency.

The digital filter introduces an extra phase delay element into

the control loop. The digital filter circuit sends the duty cycle

information to the PWM circuit at the beginning of each switch-

ing cycle (unlike an analog controller, which makes decisions on

the duty cycle information continuously). Therefore, the extra

phase delay for phase margin, Φ, introduced by the filter block is

Φ = 360 × (fC/fSW)

where:

fC is the crossover frequency.

fSW is the switching frequency.

At one-tenth the switching frequency, the phase delay is 36°. For

double update rate, the phase delay is reduced to 18°. The GUI

LPF

TRIM

DAC

ADC

50mV

–

DAC

VS ADC (12 BITS)

VOUT_OV_LIMIT

VOUT_UV_LIMIT

DPWM

REF

ADP1055

VOUT

VS+

VS–

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