ADP1055ACPZ-R7 datasheet(25/140 Pages) AD

25 / 140 page

Data Sheet

ADP1055

Rev. A | Page 25 of 140

THEORY OF OPERATION

ACCURATE PRIMARY OVERCURRENT PROTECTION

The CS1 ADC is used to measure the average value of the

primary current. The 12 MSBs of the reading (CS1_VALUE,

compared to the threshold set using the PMBus command

IIN_OC_FAULT_LIMIT (Register 0x5B) to make a fault

decision. The fault response is set by the IIN_OC_FAULT_

RESPONSE command (Register 0x5C).

PRIMARY FAST OVERCURRENT PROTECTION

The input signal on the CS1 pin is also fed into a comparator

for pulse-by-pulse OCP protection. The fast OCP comparator

is used to limit the peak primary current within each switching

cycle. Two thresholds—the 250 mV or 1.2 V threshold—are

programmable using Register 0xFE2C[2].

When the CS1 OCP threshold is crossed, the PWM outputs

(OUTA to OUTD) are immediately terminated for the remainder

of the switching cycle. For the full-bridge topology, where the

switching period is divided into two halves, a CS1 OCP event

during one half does not terminate the PWM outputs for the

second half.

The CS1 OCP comparator provides programmable blanking

and debounce to prevent false triggering; these features are

programmable using Register 0xFE4E and Register 0xFE2C.

The comparator also features a programmable timeout condition

(set in Register 0xFE4E[2:0]), which specifies that the CS1 fast

OCP condition must be present for a specified number of

consecutive switching cycles before the IIN_OC_FAST_FAULT

flag is set.

The CS1 fast OCP fault can also be set using the GPIO1

general-purpose input/output pin.

MATCHED CYCLE-BY-CYCLE CURRENT LIMIT (OCP

EQUALIZATION)

For a half-bridge converter, the cycle-by-cycle limit feature

cannot guarantee an equal duty cycle between the two half

cycles of the switching period. The imbalances of each half cycle

can cause the center point voltage of the capacitive divider to

drift from VIN/2 (half the input voltage) toward either ground or

the input voltage. This drift, in turn, can lead to output voltage

regulation failure, transformer saturation, and the doubling of

voltage stress on the synchronous rectifiers.

To avoid these problems, the ADP1055 implements a matched

cycle-by-cycle limit. This feature produces a PWM pulse width

in the second half cycle that is of equal duration as the preceding

pulse when a CS1 fast OCP event occurs (IIN_OC_FAST_

FAULT). In other words, when a cycle-by-cycle limit is triggered,

the ADP1055 forces the duty cycle in the subsequent half cycle

to be exactly the same as that of the previous half cycle.

However, if the CS1 cycle-by-cycle current limit always has the

highest priority to terminate the PWM outputs meaning that if

a cycle-by-cycle fault occurs during the period where the duty

cycle is being equalized, the cycle-by-cycle current fault takes

priority. The CS1 OCP duty cycle equalization feature (Register

0xFE57[6]) can be enabled for all topology configurations. The

edge selection is the same as for the volt-second balance feature.

LOW TEMPERATURE FILTER

During the soft start process, the soft start filter can be used in

combination with the normal mode filter and the light load mode

filter. The soft start filter can be configured as a low temperature

filter. Using Register 0xFE62[1:0], the low temperature filter is

activated on one of three selectable inputs: the external forward

temperature reading, the external reverse temperature reading,

or the rising edge of GPIO2.

The low temperature pole is activated at a temperature of 10°C;

subsequent thresholds are at 6°C, 2°C, and so on, down to −14°C

(Register 0xFE62[6:4]). The temperature hysteresis is programmed

in steps of 5°C in Register 0xFE62[3:2]. The change of filters

from one to another always takes place after a 2 sec time hysteresis

plus any other filter transition speed. It is recommended that

the ADP1055 GUI be used to program this feature. Table 6

summarizes the use of the filters for low and high temperatures.

Table 6. Filter Options for Low and High Temperatures

Load Condition

Low

Temperature

High

Temperature

Light load

Light load filter

Heavy load with low

temperature, filter

disabled

SSF/NMF with

ADD_PZ

SSF/NMF with

ADD_PZ

Heavy load with low

temperature, filter

enabled

SSF with

ADD_PZ

SSF/NMF with

ADD_PZ

VOLTAGE LOOP AUTOCORRECTION

Output voltage sampling is performed using the high speed

Nyquist ADC. The output voltage is sampled just before the end of

the switching period (tSW) or just before half the switching period

(tSW/2) if double update rate is enabled. The output voltage ripple

ramp changes as the input voltage changes, causing the sampling

voltage to also change. Assuming a steady state condition, any

dc offsets can be eliminated by sampling the output voltage

synchronously with the switching frequency.

Due to the relationship between the output voltage ripple ramp

and the input voltage, the average output voltage can drift to a

higher value when the input voltage is at its maximum value. To

correct for this drift, the ADP1055 uses a low frequency auto-

correction loop based on the LF ADC on the VS± pins. Under

ideal conditions, the voltage on this input is 1.0 V.

ADP1055ACPZ-R7 Datenblatt(PDF) 25 Page - Analog Devices

ADP1055ACPZ-R7 Datenblatt(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL