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CLC5958PCASM Datenblatt(PDF) 6 Page - National Semiconductor (TI) |
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CLC5958PCASM Datenblatt(HTML) 6 Page - National Semiconductor (TI) |
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6 / 13 page ![]() http://www.national.com 6 CLC5958 Pin Definitions AIN, AIN (Pins 13, 14) Differential inputs. Self biased at a common mode voltage of +3.25V. The ADC full scale input is 2.048Vpp differential. ENCODE, (Pins 9, 10) Differential clock inputs. ENCODE initiates a ENCODE new data conversion cycle on each rising edge. Clock signals may be sinusoidal or square waves with PECL encode levels. The falling edge of ENCODE clocks internal pipeline stages. D0-D13 (Pins 28 - 34, 39 - 45) Digital data outputs. CMOS and TTL compatible. D0 is the LSB and D13 is the inverted MSB. Output coding is two’s complement. DAV (Pin 27) Data valid. The rising edge of this signal occurs when output data is valid and may be used to latch data into following circuitry. VCM (Pin 21) Internal analog input common mode voltage reference. Nominally +3.25V. Can be used to establish the analog input common mode voltage for DC coupled applications (DC coupling not recommended, see applications section). GND (Pins 1 - 4, 8, 11, 12, 15, 19, 20, 23 - 26, 35, 36, 47, 48, and vias) circuit ground. VCC (Pins 5 - 7, 16 - 18, 22, 46) +5V power supply. Bypass each group of supply pins to ground with a 0.01 µF capacitor. DVCC (Pins 37, 38) +3.3V to +5V power supply for the digital outputs. Establishes the high output level for the digital outputs. Bypass to ground with a 0.1 µF capacitor. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CLC5958 GND GND VCC (MSB) D13 D12 D11 D10 D9 D8 D7 DVCC DVCC GND GND D6 D5 D4 D3 D2 D1 (LSB) DO DAV GND GND 1 GND 2 GND 3 GND 4 GND 5VCC 6VCC 7VCC 8 GND 9 ENCODE 10 ENCODE 11 GND 12 GND 13 AIN 14 AIN 15 GND 16 VCC 17 VCC 18 VCC 19 GND 20 GND 21 VCM 22 VCC 23 GND 24 GND vias CLC5958 Block Diagram 4-bit Flash 4-bit DAC T&H 10-bit Fine ADC Summing Network Over-range Correction Logic & Output Buffers AIN ENCODE Residue Amp |
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