CLC5958PCASM datasheet(10/13 Pages) NSC

10 / 13 page

http://www.national.com

Power Supplies

The VCC pins supply power to all of the CLC5958

circuitry with the exception of the digital output buffers.

The DVCC pins provide power to the digital output buffers.

Each supply pin should be connected to a supply (i.e. do

not leave any supply pins ﬂoating).

Local groups of supply pins should be bypassed

with.01uF capacitors. These capacitors should be placed

as close to the part as possible. Avoid using via to the

ground plane. If vias to the ground plane cannot be

avoided, then use multiple vias in close proximity to the

bypass capacitor.

The supplies should be bypassed in a manner to prevent

supply return currents from ﬂowing near the analog

inputs. The evaluation board layout is an example of how

to accomplish this.

The digital output buffer supplies (DVCC) provide a

means for programming the output buffer high level.

Supply values ranging from 3.3V to 5.0V may be applied

to these pins. In general, best performance is achieved

with DVCC set to 3.3V.

Layout Recommendations for the CSP

The 48 lead chip scale package not only provides a small

footprint, but also provides an excellent connection to

ground. The thermal vias on the bottom of the package

also serve as additional ground pads. The solder pad

dimensions on the pc board should match the package

pads 1:1.

Soldering Recommendations for the CSP

A 4 mil thick stencil for the solder screen printing is

recommended. The suggested IR reﬂow proﬁle is:

Ramp Up:

2°C/sec

Dwell Time > 183°C:

75 sec

Solder Temperature:

215°C

(max solder temperature):

235°C

Dwell Time @ Max Temp:

5 sec

Ramp Down:

2°C/sec

Description

The CLC5958 evaluation printed circuit board provides a

convenient test bed for rapid evaluation of the CLC5958.

It illustrates the proper approach to layout in order to

achieve best performance, and provides a performance

benchmark.

Analog Input

The CLC5958 evaluation board is conﬁgured to be driven

by a single-ended signal at the AIN SMA connector (the

AIN connector is disconnected). The AIN SMA

connector should

driven

from

Ω source

impedance. A full scale input is approximately 1.4Vpp

(7dBm). The single-ended input is converted to a

differential input by an on-board transformer.

When performing sine wave testing, it is critical that the

input sine wave be ﬁltered to remove harmonics and

source noise.

Encode Input

The CLK SMA connector is the encode input and should

also be driven from a 50

Ω source. A low jitter 16dBm sine

wave should be applied at this input. In some cases it

may be necessary to band-pass ﬁlter the sine wave in

order to achieve low jitter.

The single-ended clock input is converted to a differential

signal by an on-board transformer and buffered by an

ECL buffer.

Digital Outputs

The digital outputs are available at the Eurocard

connector (J1). Data bits D0 through D13 are available at

J1 pins 18B through 5B. The data ready signal (labeled

DR in the schematic) is available at J1 pin 20B. These

outputs are also available at the HP 01650-63203

termination adapter for direct connection to an HP logic

analyzer (see evaluation board schematic). The outputs

are buffered by 3.3V digital latches. The falling edge of

the data ready signal may be used to latch the output data.

Supply Voltages

Power is sourced to the board through the Eurocard con-

nector. A 5V supply should be connected at J1 pins 32A

and 32B. A 3.3V supply should be connected at J1 pins

31A and 31 B. The ground return for these supplies is at

J1 pins 27A, 27B, 28A, and 28B. It is recommended that

low noise linear supplies be used.

CLC5958 Evaluation Board

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