CLC5958PCASM datasheet(8/13 Pages) NSC

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Driving the Analog Inputs

The differential analog inputs, AIN and AIN, are biased

from an internal 3.25V reference (a 2.4V bandgap

reference plus a diode) through an on-chip resistance of

500

Ω. This bias voltage is set for optimum performance,

and varies with temperature. Since DC coupling the

inputs overrides the internal common mode voltage, it is

recommended that the inputs to the CLC5958 be AC

coupled whenever possible. The time constant of the

input coupling network must be greater than 1

µsec to

minimize distortion due to nonlinear input bias currents.

Additionally, the common mode source impedance

should be less than 100

Ω at the sample rate.

If DC coupling is required, then the VCM output may be

used to establish the input common mode voltage. The

CLC5958 samples the common mode voltage at the

internal track-and-hold output and servos the VCM output

to establish the optimum common mode potential at the

track-and-hold. It is possible to use the VCM output to

construct an external servo loop.

Figure 1 below illustrates one input coupling method. The

transformer

provides

noiseless

single-ended

differential conversion. The two 50

Ω resistors in the

secondary deﬁne the input impedance and provide a low

common mode source impedance through the bypass

capacitors.

Figure 1: Input Coupling

Alternatively, the inputs can be driven using a differential

ampliﬁer as shown in Figure 2.

The network of Figure 2 uses a simple RC low-pass ﬁlter

to roll off the noise of the differential ampliﬁer. The net-

work has a cutoff frequency of 40MHz. Different noise

ﬁlter designs are required for different applications. For

example, an IF application would require a band-pass

noise ﬁlter.

The analog input lines should be routed close together so

that any coupling from other sources is common mode.

Figure 2: Differential Ampliﬁer

Driving the ENCODE Inputs

The ENCODE and ENCODE inputs are differential clock

inputs that are referenced to VCC. They may be driven

with PECL input levels. Alternatively they may be driven

with a differential input (e.g. a sine input) that is centered

at 1.2 Volts below VCC and which meets the min and max

ratings for VIL and VIH. Low noise differential clock signals

provide the best SNR performance for the converter.

The ENCODE inputs are not self biasing, so a DC bias

current path must be provided to each of the inputs.

Figure 3 shows one method of driving the encode inputs.

Figure 3: ENCODE Inputs

The transformer converts the single-ended clock signal to

a differential signal. The center-tap of the secondary is

biased by the VBB potential of the ECL buffer. The diodes

in the secondary limit the input swing to the buffer.

Since the encode inputs are close to the analog inputs, it

is recommended that the analog inputs be routed on the

top of the board directly over a ground plane and that the

encode lines be routed on the back of the board and then

connected through via to the encode inputs.

Latching the Output Data

The rising edge of DAV is approximately centered in the

data transition window, and may be used to latch the

output data. The DAV output has twice the load driving

capability of the data outputs so that two latch clock

inputs may be driven by this output.

CLC5958 Application Information

VIN

AIN

CLC5958

0.1

0.01

0.1

1:1.4

AIN

CLC5958

39pf

0.1

100

VIN

ENCODE

CLC5958

332

VBB

Clock

0.1

1:1

0.1

MC10EL16

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