ADS5500MPAPREP datasheet(24/37 Pages) TI1

24 / 37 page

ADS5500-EP

SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008

www.ti.com

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5500 is a low-power, 14-bit, 125−MSPS,

CMOS,

switched−capacitor,

pipeline

ADC

that

operates from a single 3.3-V supply. The conversion

process is initiated by a falling edge of the external input

clock. Once the signal is captured by the input S&H, the

input sample is sequentially converted by a series of

small resolution stages, with the outputs combined in a

digital correction logic block. Both the rising and the

falling clock edges are used to propagate the sample

through the pipeline every half clock cycle. This process

results in a data latency of 16.5 clock cycles, after which

the output data is available as a 14-bit parallel word,

coded in either straight offset binary or binary

twos−complement format.

INPUT CONFIGURATION

The analog input for the ADS5500 consists of a

differential architecture implemented using a switched

capacitor technique, shown in Figure 5.

1,L2 : 6nh to 10nh effective

1a,R1b :25W to 35W

1a,C1b : 2.2pF to 2.6pF

1,CP2 : 2.5pF to 3.5pF

3,CP4,: 1.2pF to 1.8pF

ACROSS :0.8pF to 1.2pF

3 :80W to 120W

Switches:

All switches are on in sample phase.

Approximately half of every clock period is a sample phase.

1a,W1b : On Resistance: 25W to 35W

2 : On Resistance: 7.5W to 15W

3a,W3b : On Resistance: 40W to 60W

1a,W1b,W2,W3a,W3b : Off Resistance: 1e10

ACROSS

SAMPLE

PHASE

SAMPLE

PHASE

SWITCH

SAMPLE

PHASE

VINCM

SAMPLE

PHASE

SAMPLE

PHASE

INP

INM

Figure 5. Analog Input Stage

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