ADS5500MPAPREP datasheet(27/37 Pages) TI1

27 / 37 page

ADS5500-EP

SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008

www.ti.com

POWER DOWN

The device enters power down in one of two ways −

either by reducing the clock speed to between dc and

1 MHz, or by setting a bit through the serial

programming interface. Using the reduced clock speed,

the power down may be initiated for clock frequencies

below 10 MHz. For clock frequencies between 1 MHz

and 10 MHz, this can vary from device to device, but will

power down for clock speeds below 1 MHz.

The device can be powered down by programming the

internal register (see Serial Programming Interface

section). The outputs become 3-stated and only the

internal reference is powered up to shorten the

power-up time. The power-down mode reduces power

dissipation to a minimum of 180 mW.

REFERENCE CIRCUIT

The

ADS5500

has

built-in

internal

reference

generation, requiring no external circuitry on the printed

circuit board (PCB). For optimum performance, it is best

to connect both REFP and REFM to ground with a 1−

µF

decoupling capacitor in series with a 1-

Ω resistor (see

Figure 9). In addition, an external 56.2-k

Ω resistor

should be connected from IREF (pin 31) to AGND to set

the proper current for the operation of the ADC (see

Figure 9). No capacitor should be connected between

pin 31 and ground; only the 56.2-k

Ω resistor should be

used.

REFP

REFM

IREF

56k

Figure 9. REFP, REFM, and IREF Connections for

Optimum Performance

CLOCK INPUT

The ADS5500 clock input can be driven with either a

differential clock signal or a single-ended clock input,

with little or no difference in performance between both

configurations. The common-mode voltage of the clock

inputs is set internally to CM (pin 17) using internal 5-k

Ω

resistors that connect CLKP (pin 10) and CLKM (pin 11)

to CM (pin 17) (see Figure 10).

CLKM

CLKP

6pF

3pF

Figure 10. Clock Inputs

When driven with a single-ended CMOS clock input, it

is best to connect CLKM (pin 11) to ground with a

0.01-

µF capacitor, while CLKP is ac coupled with a

0.01-

µF capacitor to the clock source (see Figure 11).

0.01

CLKP

ADS5500

CLKM

Square Wave

or Sine Wave

(3V

PP)

Figure 11. AC-Coupled Single-Ended Clock Input

The ADS5500 clock input can also be driven

differentially, reducing susceptibility to common-mode

noise. In this case, it is best to connect both clock inputs

to the differential input clock signal with 0.01-

µF

capacitors (see Figure 12).

0.01

CLKP

ADS5500

CLKM

0.01

Differential Square Wave

or Sine Wave

(3V

PP)

Figure 12. AC-Coupled Differential Clock Input

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