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ADS5500MPAPREP Datenblatt(PDF) 13 Page - Texas Instruments

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Teilenummer ADS5500MPAPREP
Bauteilbeschribung  Analog-To-Digital Converter
PDF  37 Pages
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Hersteller  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS5500MPAPREP Datenblatt(HTML) 13 Page - Texas Instruments

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ADS5500-EP
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
www.ti.com
13
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB
Aperture Delay
The delay in time between the falling edge of the input
sampling clock and the actual time at which the sampling
occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Width/Duty Cycle
A perfect differential sine−wave clock results in a 50%
clock duty cycle on the internal coversion clock. Pulse
width high is the minimum amount of time that the
ENCODE pulse should be left in logic 1 state to achieve
rated performance. Pulse width low is the minimum time
that the ENCODE pulse should be left in a low state (logic
0). At a given clock rate, these specifications define an
acceptable clock duty cycle.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly one
LSB apart. DNL is the deviation of any single LSB
transition at the digital output from an ideal one LSB step
at the analog input. If a device claims to have no missing
codes, it means that all possible codes (for a 14-bit
converter, 16384 codes) are present over the full operating
range.
Effective Number of Bits (ENOB)
The effective number of bits for a sine−wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
ENOB
+ SINAD * 1.76
6.02
If SINAD is not known, SNR can be used exceptionally to
calculate ENOB (ENOBSNR).
Effective Resolution Bandwidth
The highest input frequency where the SNR (dB) is
dropped by 3 dB for a full-scale input amplitude
Gain Error
The amount of deviation between the ideal transfer
function and the measured transfer function (with the offset
error removed) when a full-scale analog input voltage is
applied to the ADC, resulting in all ones in the digital code.
Gain error is usually given in LSB or as a percent of
full-scale range (%FSR).
Integral Nonlinearity (INL)
The deviation of the transfer function from a reference line
measured in fractions of one LSB using a best straight line
or best fit determined by a least square curve fit. INL is
independent from effects of offset, gain, or quantization
errors.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
This is the maximum sampling rate where certified
operation is given.
Minimum Conversion Rate
The minimum sampling rate where the ADC still works.
Nyquist Sampling
When the sampled frequencies of the analog input signal
are below fCLOCK/2, it is called Nyquist sampling. The
Nyquist frequency is fCLOCK/2, which can vary depending
on the sample rate (fCLOCK).
Offset Error
The deviation of output code from mid-code when both
inputs are tied to common-mode
Propagation Delay
The delay between the input clock rising edge and the time
when all data bits are within valid logic levels
Signal-to-Noise and Distortion (SINAD)
The RMS value of the sine wave fIN (input sine wave for an
ADC) to the RMS value of the noise of the converter from
DC to the Nyquist frequency, including harmonic content.
It is typically expressed in decibels (dB). SINAD includes
harmonics, but excludes DC.
SINAD
+ 20Log
(10)
Input(V
S )
Noise
) Harmonics
Signal-to-Noise Ratio (Without Harmonics)
SNR is a measure of signal strength relative to background
noise. The ratio is usually measured in dB. If the incoming
signal strength in
µV is VS, and the noise level (also in µV)
is VN, the SNR in dB is given by the formula:
SNR
+ 20Log
(10)
V
S
V
N
This is the ratio of the RMS signal amplitude, VS (set one
dB below full-scale), to the RMS value of the sum of all
other spectral components, VN, excluding harmonics and
dc.



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