ADS5500-EP

SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008

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8

TIMING CHARACTERISTCS

16.5 Clock Cycles

Input Clock

Output Clock

Data Out

(D0−D13)

Analog

Input

Signal

Sample

N

N+ 1

N+ 2

N+ 3

N+ 4

N+ 15

N+ 16

N+ 17

N

- 17

N

- 16

N

- 15

N

- 13

N

- 3N - 2N - 1N

tA

tSETUP

tHOLD

Data Invalid

tPDI

NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing

matches closely with the specified values.

Figure 2. Timing Diagram

Typ, min, and max values at TA = 25°C, min and max specified over the full recommended operating temperature range,

AVDD = DRVDD = 3.3 V, 3−VPP differential clock, and CLOAD = 10 pF (unless otherwise noted)

PARAMETER

DESCRIPTION

TYP

UNIT

Switching Specification

Aperture delay, tA

Input CLK falling edge to data sampling point

1

ns

Aperture jitter (uncertainty)

Uncertainty in sampling instant

300

fs

Data setup time, tSU

Data valid(2) to 50% of CLKOUT rising edge

2.5

ns

Data hold time, th

50% of CLKOUT rising edge to data becoming invalid(2)

2.1

ns

Input clock to output data valid

start(3)(4), tSTART

Input clock rising edge to Data valid start delay

2.2

ns

Input clock to output data valid

end(3)(4), tEND

Input clock rising edge to Data valid end delay

6.9

ns

Output clock jitter, tJIT

Uncertainty in CLKOUT rising edge, peak−to−peak

150

ps

Output clock rise time, tr

Rise time of CLKOUT measured from 20% to 80% of

DRVDD

1.7

ns

Output clock fall time, tf

Fall time of CLKOUT measured from 80% to 20% of

DRVDD

1.5

ns

Input clock to output clock delay,

tPDI

Input clock rising edge, zero crossing, to output clock

rising edge 50%

4.8

ns

Data rise time, tr

Data rise time measured from 20% to 80% of DRVDD

3.6

ns

Data fall time, tf

Data fall time measured from 80% to 20% of DRVDD

2.8

ns

Latency Time for a sample to

propagate to the ADC outputs

17.5 clock cycles

17.5

Clock Cycles

(1) Timing parameters are ensured by design and characterization and not tested in production.

(2) Data valid refers to 2 V for LOGIC high and 0.8 V for LOGIC low.

(2) See the Output Information section for details on using the input clock for data capture.

(4) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add one−half clock period for the valid number

for a falling−edge CLKOUT polarity.