AD15700SLASHPCB datasheet(32/44 Pages) AD

32 / 44 page

REV. A

–32–

AD15700

PARALLEL INTERFACE

The ADC is configured to use the parallel interface when the

SER/

PAR is held low. The data can be read either after each

conversion, which is during the next acquisition phase, or during

the following conversion as shown, respectively, in Figures 18

and 19. When the data is read during the conversion, however, it

is recommended that it be read only during the first half of the

conversion phase. That avoids any potential feedthrough between

voltage transients on the digital interface and the most critical

analog conversion circuitry.

CURRENT

CONVERSION

CSZ_ADC

BUSY

DATA BUS

Figure 17. Slave Parallel Data Timing for Reading

(Read after Convert)

CONVERSION

CS_ADC = 0

CNVST, RD

BUSY

DATA BUS

Figure 18. Slave Parallel Data Timing for Reading

(Read during Convert)

The BYTESWAP pin allows a glueless interface to an 8-bit bus.

As shown in Figure 19, the LSB byte is output on D[7:0] and

the MSB is output on D[15:8] when BYTESWAP is low. When

BYTESWAP is high, the LSB and MSB are swapped and the

LSB is output on D[15:8] and the MSB is output on D[7:0]. By

connecting BYTESWAP to an address line, the 16 data bits can

be read in two bytes on either D[15:8] or D[7:0].

HIGH BYTE

LOW BYTE

CS_ADC

HIGH BYTE

LOW BYTE

HI-Z

BYTE

PINS D[15.8]

PINS D[7.0]

Figure 19. 8-Bit Parallel Interface

SERIAL INTERFACE

The ADC is configured to use the serial interface when the

SER/

PAR is held high. The ADC outputs 16 bits of data, MSB

first, on the SDOUT pin. This data is synchronized with the

16 clock pulses provided on the SCLK pin. The output data is

valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE

Internal Clock

The ADC is configured to generate and provide the serial data

clock SCLK when the EXT/INT pin is held low. It also generates

a SYNC signal to indicate to the host when the serial data is valid.

The serial clock SCLK and the SYNC signal can be inverted if

desired. Depending on RDC/SDIN input, the data can be read

after each conversion or during conversion. Figures 20 and 21

show the detailed timing diagrams of these two modes.

Usually, because the ADC is used with a fast throughput, the

mode master read during conversion is the most recommended

serial mode when it can be used.

In read during conversion mode, the serial clock and data toggle at

appropriate instants, which minimizes potential feedthrough

between digital activity and the critical conversion decisions.

In read after conversion mode, it should be noted that unlike in

other modes, the signal BUSY returns low after the 16 data bits

are pulsed out and not at the end of the conversion phase, which

results in a longer BUSY width.

SLAVE SERIAL INTERFACE

External Clock

The ADC is configured to accept an externally supplied serial

data clock on the

SCLK pin when the EXT/INT pin is held

high. In this mode, several methods can be used to read the data.

The external serial clock is gated by

CS_ADC and the data are

output when both

CS_ADC and RD are low. Thus, depending on

CS_ADC, the data can be read after each conversion or during

the following conversion. The external clock can be either a

continuous or discontinuous clock. A discontinuous clock can be

either normally high or normally low when inactive. Figure 22 and

Figure 24 show the detailed timing diagrams of these methods.

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